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    ELECTRONIC COMPONENT MOUNTING MODULE HAVING BUS BAR STACK, AND METHOD FOR MANUFACTURING SAME
    1.
    发明公开
    ELECTRONIC COMPONENT MOUNTING MODULE HAVING BUS BAR STACK, AND METHOD FOR MANUFACTURING SAME 审中-实审

    公开(公告)号：EP4435814A1

    公开(公告)日：2024-09-25

    申请号：EP22892937.8

    申请日：2022-11-15

    Applicant: Nippon Chemi-Con Corporation

    Inventor： IDEUE Takashi ,  KUROSU Mitsuru

    IPC: H01G13/00 ,  H01G2/02 ,  H01G4/228 ,  H01G4/38

    CPC classification number: H01G2/02 ,  H01G4/38 ,  H01G4/228 ,  H01G13/00

    Abstract: Provided are a surface mounting type electronic component mounting module using a bus bar, wherein the heights of solder mounting surfaces of a laminated bus bar of an anode and a laminated bus bar of a cathode are aligned to enable the use of reflow solder, and a more space-saving and miniaturized electronic component mounting module without lowering electrical characteristics. An electronic component mounting module is provided with a bus bar laminate in which a first bus bar and a second bus bar, each of which is provided with a region for soldering an external terminal of an electronic component, are laminated in an insulated manner, wherein the first bus bar is provided with an opening, the second bus bar is provided with a convex body projecting toward the first bus bar side and including a region for soldering, the convex body of the second bus bar is arranged at a position corresponding to the opening, the region for soldering the first bus bar and the region for soldering the convex body are set to have the same height as to such an extent that an external terminal of the electronic component by reflow soldering can be soldered, a plurality of electronic components to which the external terminals are soldered are provided on the first bus bar side, and the plurality of electronic components are connected to one convex body by external terminals of the same polarity.

    COMPOSITE CAPACITOR
    5.
    发明公开
    COMPOSITE CAPACITOR 审中-实审

    公开(公告)号：EP4376037A1

    公开(公告)日：2024-05-29

    申请号：EP22845767.7

    申请日：2022-06-30

    Applicant: Nichicon Corporation

    Inventor： MORI, Takashi ,  NOSE, Takashi

    IPC: H01G4/38 ,  H01G2/10 ,  H01G4/228 ,  H01G4/32

    CPC classification number: H01G4/38 ,  H01G4/228 ,  H01G4/32 ,  H01G2/10 ,  Y02E60/13

    Abstract: To provide a composite capacitor that withstands higher voltages and handles the high-frequency operations of switching elements. In a main capacitor 10 formed of a metallized film, first and second plate conductor terminals 12c, 13c as cathode and anode are continuously connected to first and second plate conductor bodies 12a, 13a. In a parallel plate sub-capacitor 20, a sheet dielectric 21 is inserted into a gap between opposed first and second electrode plate bodies 22a, 23a. First and second electrode plate terminals 22c, 23c are continuously connected to the first and second electrode plate bodies 22a, 23a. The main capacitor 10 and the sub-capacitor 20 are disposed in close proximity to each other. The first and second plate conductor terminals 12c, 13c and the first and second electrode plate terminals 22c, 23c can be connected to each other by the terminals of the same polarity.

    MULTI-DIE FINE GRAIN INTEGRATED VOLTAGE REGULATION
    9.
    发明公开
    MULTI-DIE FINE GRAIN INTEGRATED VOLTAGE REGULATION 审中-公开

    公开(公告)号：EP4006972A3

    公开(公告)日：2022-12-28

    申请号：EP22150527.4

    申请日：2014-07-29

    Applicant: Apple Inc.

    Inventor： ZERBE, Jared L. ,  FANG, Emerson S. ,  ZHAI, Jun ,  SEARLES, Shawn

    IPC: H01L25/16 ,  H01L23/64 ,  H01G4/228 ,  H01G4/232 ,  H01L49/02 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

    Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device (120) may include one or more current consuming elements. A passive device (100) may be coupled (110) to the power consuming device. The passive device includes a plurality of passive elements formed on a semiconductor substrate. The passive elements are arranged in an array of structures (102) on the semiconductor substrate. The power consuming device and the passive device are coupled using one or more terminals (110). The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

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