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    SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
    3.
    发明公开
    SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION 审中-公开

    公开(公告)号：EP4345870A1

    公开(公告)日：2024-04-03

    申请号：EP23190856.7

    申请日：2023-08-10

    申请人： INTEL Corporation

    发明人： GULER, Leonard P. ,  HARAN, Mohit K. ,  MEHTA, Nikhil ,  WALLACE, Charles H. ,  GHANI, Tahir ,  YEMENICIOGLU, Sukru

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    摘要： Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：EP4210094A1

    公开(公告)日：2023-07-12

    申请号：EP22204986.8

    申请日：2022-11-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： KIM, Kyung Wook ,  YOO, Seung Yong ,  LEE, Eui Bok ,  KIM, Jin Nam ,  JUNG, Eun-Ji

    IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/532

    摘要： A semiconductor device is provided. The semiconductor device includes: a lower line structure; an upper interlayer insulating film provided on the lower line structure and having a trench formed therein, wherein the trench includes a wiring line trench and a via trench extending from the wiring line trench to the lower line structure; and an upper line structure provided in the line trench, wherein the upper line structure includes an upper barrier film and an upper filling film. The upper filling film includes a first sub-filling film in contact with the upper interlayer insulating film, and a second sub-filling film provided on the first sub-filling film. The first sub-filling film fills an entirety of the upper via trench and covers at least a portion of a bottom surface of the upper wiring line trench.

    SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER
    7.
    发明公开
    SYSTEMS AND METHODS FOR GRAPHENE BASED LAYER TRANSFER 审中-公开

    公开(公告)号：EP4105966A3

    公开(公告)日：2023-06-21

    申请号：EP22179687.3

    申请日：2016-09-08

    申请人： Massachusetts Institute Of Technology

    发明人： KIM, Jeehwan

    IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L29/04

    摘要： A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.