Power supply device
    72.
    发明专利
    Power supply device 有权
    电源设备

    公开(公告)号:JP2012205331A

    公开(公告)日:2012-10-22

    申请号:JP2011065231

    申请日:2011-03-24

    Inventor: NAKAGAWA SHIGEO

    CPC classification number: H02M3/156 H02M3/1588 H02M7/53803 Y02B70/1466

    Abstract: PROBLEM TO BE SOLVED: To provide a power supply device that reconciles suppressed EMI noise and a reduced output voltage ripple.SOLUTION: In the power supply device, a switching control device 101 for controlling switching elements with a pulse control signal includes a PPM circuit 107 for modulating pulse position, a PWM circuit 106 for modulating pulse width, and a pulse generation circuit 109 for generating a pulse modulated by the PPM circuit 107 and the PWM circuit 106. When pulses subjected to pulse position modulation by the PPM circuit 107 have coarser pulse intervals than before modulation, the PWM circuit 106 lengthens the pulse width. When the pulses subjected to pulse position modulation by the PPM circuit 107 have closer pulse intervals than before modulation, on the other hand, the PWM circuit 106 shortens the pulse width.

    Abstract translation: 要解决的问题:提供调节抑制的EMI噪声和降低的输出电压纹波的电源装置。 解决方案:在电源装置中,用于通过脉冲控制信号控制开关元件的开关控制装置101包括用于调制脉冲位置的PPM电路107,用于调制脉冲宽度的PWM电路106和脉冲发生电路109 用于产生由PPM电路107和PWM电路106调制的脉冲。当由PPM电路107进行脉冲位置调制的脉冲具有比调制之前更大的脉冲间隔时,PWM电路106延长脉冲宽度。 当由PPM电路107进行脉冲位置调制的脉冲具有比调制之前更近的脉冲间隔时,另一方面,PWM电路106缩短脉冲宽度。 版权所有(C)2013,JPO&INPIT

    Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
    77.
    发明专利
    Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp 有权
    三相功率MOSFET开关用作同步整流器或电压钳

    公开(公告)号:JP2012169650A

    公开(公告)日:2012-09-06

    申请号:JP2012089822

    申请日:2012-04-11

    Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET switch suitable for use as a synchronous rectifier in a power converter.SOLUTION: An N-channel power MOSFET with its source and body connected together and biased at a high positive voltage with respect to its drain is fabricated. A gate is controlled by a switch (1184) which selectively connects the gate to the source or to a voltage (VCP) enough to turn a channel of the MOSFET fully on. When the gate is connected to the source, the device functions as a "pseudo-Schottky" diode which turns on at a lower voltage and has a lower conductor resistance than a conventional PN junction. When the gate is connected to the positive voltage the channel of the MOSFET is turned fully on. This MOSFET switch reduces power loss and stored charge in the "break-before-make" time.

    Abstract translation: 要解决的问题:提供一种适用于功率转换器中的同步整流器的MOSFET开关。 解决方案:制造其源极和主体连接在一起并相对于其漏极偏置在高正电压的N沟道功率MOSFET。 栅极由开关(1184)控制,开关选择性地将栅极连接到源极或者将电压(VCP)足以使MOSFET的通道完全导通。 当栅极连接到源极时,该器件用作“伪肖特基”二极管,其在较低电压下导通,并且具有比常规PN结更低的导体电阻。 当栅极连接到正电压时,MOSFET的通道完全导通。 该MOSFET开关在“断开”制造时间内减少了功率损耗和存储电荷。 版权所有(C)2012,JPO&INPIT

    Dc-dc converter
    78.
    发明专利
    Dc-dc converter 有权
    DC-DC转换器

    公开(公告)号:JP2012147552A

    公开(公告)日:2012-08-02

    申请号:JP2011003042

    申请日:2011-01-11

    Inventor: GOTO YUICHI

    CPC classification number: H02M3/1588 H02M2001/0003 Y02B70/1466

    Abstract: PROBLEM TO BE SOLVED: To provide a power-efficient DC-DC converter.SOLUTION: The DC-DC converter includes a low side switch Q2 connected in series with a high side switch Q1, a high side control circuit 6, and a low side control circuit 7. The high side control circuit 6 turns on or off and PWM-controls the high side switch Q1. The low side control circuit 7 has a first detection circuit 3 for detecting a current through the low side switch Q2, and an offset cancellation circuit 14 for holding an output of the first detection circuit 3 as an offset voltage when the low side switch Q2 is off, and outputting a value resulting from the subtraction of the offset voltage from an output of the first detection circuit 3 when the low side switch Q2 is on. The low side control circuit 7 turns on the low side switch Q2 when the high side switch Q1 is off, and turns off the low side switch Q2 by comparing an output voltage of the offset cancellation circuit 14 with a reference voltage.

    Abstract translation: 要解决的问题:提供功率高效的DC-DC转换器。 解决方案:DC-DC转换器包括与高侧开关Q1,高侧控制电路6和低侧控制电路7串联连接的低侧开关Q2。高侧控制电路6接通或 并且PWM控制高侧开关Q1。 低侧控制电路7具有用于检测通过低侧开关Q2的电流的第一检测电路3以及当低侧开关Q2为低电平时,将第一检测电路3的输出保持为偏移电压的偏移抵消电路14 关闭,并且当低侧开关Q2导通时,从第一检测电路3的输出输出从偏移电压减去的值。 当低侧开关Q1断开时,低侧控制电路7接通低侧开关Q2,并通过将偏移抵消电路14的输出电压与参考电压进行比较来关断低侧开关Q2。 版权所有(C)2012,JPO&INPIT

    Comparator, control circuit for switching regulator using the same, switching regulator, and electronic apparatus
    79.
    发明专利
    Comparator, control circuit for switching regulator using the same, switching regulator, and electronic apparatus 有权
    比较器,用于切换调节器的控制电路,开关稳压器和电子设备

    公开(公告)号:JP2012129645A

    公开(公告)日:2012-07-05

    申请号:JP2010277374

    申请日:2010-12-13

    Inventor: OYAMA MANABU

    CPC classification number: H02M3/1588 H02M2001/0032 Y02B70/1466 Y02B70/16

    Abstract: PROBLEM TO BE SOLVED: To provide a comparator that has new output logic.SOLUTION: A comparator 100 compares an input voltage Vwith a reference voltage V. A differential amplification circuit 10 comprises: a first input transistor Mi1 having a control terminal with the reference voltage Vapplied; and a second input transistor Mi2 having a control terminal with the input voltage Vapplied. An output stage 20 receives an output signal Vof the differential amplification circuit 10 to output a corresponding signal as an output signal Sindicative of the result of comparison. A feedback circuit 30 receives the output signal Sof the output stage 20, and if the output signal Stransitions from a first level to a second level, feeds it back to the differential amplification circuit 10 or the output stage 20 to return the output signal Sto the first level.

    Abstract translation: 要解决的问题:提供具有新输出逻辑的比较器。

    解决方案:比较器100将输入电压V IN 与参考电压V REF 进行比较。 差分放大电路10包括:具有施加参考电压V REF 的控制端子的第一输入晶体管Mi1; 并且施加具有输入电压V IN 的控制端子的第二输入晶体管Mi2。 输出级20接收差分放大电路10的输出信号V x“,输出相应的信号作为输出信号S OUT 表示比较结果。 反馈电路30接收输出级20的输出信号S OUT ,如果输出信号S OUT 从a 第一电平到第二电平,将其馈送到差分放大电路10或输出级20,以将输出信号S OUT 返回到第一电平。 版权所有(C)2012,JPO&INPIT

    Low voltage power supply
    80.
    发明专利

    公开(公告)号:JP2012510251A

    公开(公告)日:2012-04-26

    申请号:JP2011537530

    申请日:2009-11-16

    CPC classification number: H02M1/08 H02M3/1588 Y02B70/1466

    Abstract: 入力DC電圧V
    + を出力DC電圧レベルに変換するバックレギュレータは、DC電圧レベルを出力する結合インダクタと、出力DC電圧レベルの誤差を感知するオペアンプと、誤差に対応するデューティサイクルを有するパルス波形を提供するパルス幅変調器(PWM)として動作するコンパレータとを含む。 パルス波形に応答してV
    + 電圧レベルを出力するV
    + 電圧ドライバと、パルス波形に応答してV
    + 電圧レベルよりも高く、V
    + 電圧レベルを補完するスーパー電圧レベルVssを出力するVss電圧ドライバとを含む。 スーパー電圧レベル、及びV
    + 電圧レベルをそれぞれ受信するゲートを有し、結合インダクタを駆動して、DC電圧レベルを出力するデュアルMOSFETを含む。 PWMと電圧ドライバとの間に結合されるパルス整形器は、パルス波形より立ち上がり時間が速く、電圧ドライバ駆動用制御信号として提供されるシャープなパルスを形成する。
    【選択図】図2

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