公开(公告)号：JP4605608B2

公开(公告)日：2011-01-05

申请号：JP2007058251

申请日：2007-03-08

Applicant: 南亞電路板股▲ふん▼有限公司

Inventor： 何信芳 ,  林賢傑 ,  江國春 ,  羅興倫

IPC: H05K1/02

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K2201/09481 ,  H05K2201/09927

公开(公告)号：JP4895295B2

公开(公告)日：2012-03-14

申请号：JP2007058217

申请日：2007-03-08

Applicant: 南亞電路板股▲ふん▼有限公司

Inventor： 何信芳 ,  林賢傑 ,  江國春 ,  黄振宏

IPC: H01L23/12

CPC classification number: H01L23/5389 ,  H01L23/36 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.