-
公开(公告)号：JP5596812B2
公开(公告)日：2014-09-24
申请号：JP2013070935
申请日：2013-03-29
Applicant: 株式会社日立ハイテクノロジーズ
IPC: G01N23/225 , H01L21/66
Abstract: PROBLEM TO BE SOLVED: To solve the problem that, although there has been a method for evaluating pattern shapes of electronic devices by using design data or a non-defective pattern as a reference pattern, the pattern shape cannot be evaluated with high accuracy because it is difficult to correctly define a shape suitable for manufacturing conditions of the electronic devices by the design data or the non-defective pattern.SOLUTION: A shape evaluation method of circuit patterns of electronic devices comprises: means for generating contour distribution data of the circuit patterns from contour data of at least two or more circuit patterns; means for generating a reference pattern used for pattern shape evaluation, from the contour distribution data; and means for evaluating the pattern shape by comparing an evaluation target pattern with the reference pattern.
-
公开(公告)号：JP5276854B2
公开(公告)日：2013-08-28
申请号：JP2008031314
申请日：2008-02-13
Applicant: 株式会社日立ハイテクノロジーズ
IPC: H01L21/66 , G01N23/225
CPC classification number: G06K9/00 , G01R31/31813 , G06K9/6255 , G06T7/001 , G06T2207/30141
Abstract: Although there has been a method for evaluating pattern shapes of electronic devices by using, as a reference pattern, design data or a non-defective pattern, the conventional method has a problem that the pattern shape cannot be evaluated with high accuracy because of the difficulty in defining an exact shape suitable for the manufacturing conditions of the electronic devices. The present invention provides a shape evaluation method for circuit patterns of electronic devices, the method including a means for generating contour distribution data of at least two circuit patterns from contour data sets on the circuit patterns; a means for generating a reference pattern used for the pattern shape evaluation, from the contour distribution data; and a means for evaluating the pattern shape by comparing each evaluation target pattern with the reference pattern.
-
公开(公告)号：JPWO2016002341A1
公开(公告)日：2017-06-01
申请号：JP2016531172
申请日：2015-05-11
Applicant: 株式会社日立ハイテクノロジーズ
CPC classification number: G01B15/00 , G01B15/04 , H01J37/222 , H01J37/28 , H01J2237/2817 , H01L22/12
Abstract: 本発明は、パターンの深さ方向の測定を高精度に実現するパターン測定方法、及びパターン測定装置の提供を目的とする。本発明では、集束イオンビームの照射によって、深穴、深溝、或いは立体構造を有する回路素子を含む試料領域に傾斜面を形成し、傾斜面と試料表面との間の境界を含むように、走査電子顕微鏡の視野を設定し、当該視野への電子ビームの走査によって得られる検出信号に基づいて、前記視野の画像を取得し、当該取得された画像を用いて、傾斜面と非傾斜面の境界となる第1の位置と、傾斜面内に位置する所望の深穴または深溝の位置である第2の位置を特定し、当該第1の位置と第2の位置との間の前記試料表面方向の寸法と、前記斜面の角度に基づいて、前記深穴、深溝、或いは立体構造を有する回路素子を構成するパターンの高さ方向の寸法を求めるステップを有するパターン測定方法、及び個の測定を実現する装置を提案する。
-
-
-
Search Results
4
records
(took 0.021 seconds)
