公开(公告)号：JP2000304630A

公开(公告)日：2000-11-02

申请号：JP11105699

申请日：1999-04-19

Applicant: DENSO CORP

Inventor： HIRAMATSU TOMOYUKI ,  SONOBE TOSHIO

IPC: H01L23/12 ,  G01L1/00 ,  G06F17/50

Abstract: PROBLEM TO BE SOLVED: To make precisely analyzable the thermal strain simulation of a solder bonding part and the life prediction in a short time by using a structure model mounting BGA/CSP onto a printed wiring board. SOLUTION: In this analyzing method, the actually mounted state on a printed wiring board of a semiconductor package wherein a plurality of solder bumps arranged in a lattice form are formed on an interposer for semiconductor chip mounting is made, to be a structure model, and the method consists of a process S1 for setting a two-dimensional model on the basis of a section corresponding to the breakdown mode of a solder bonding part in a practical temperature cycle test, processes S2-S4 for calculating plastic strain generated in the solder bonding part, by performing finite element method analysis based on the two-dimensional model, and processes for predicting the thermal fatigue life of the solder bonding part, on the basis of an S-N curve showing the relation between the calculated plastic strain and the thermal fatigue life of the solder bonding part which is obtained from the practical temperature cycle test.

公开(公告)号：JP2008002869A

公开(公告)日：2008-01-10

申请号：JP2006170954

申请日：2006-06-21

Applicant: Denso Corp ,  株式会社デンソー

Inventor： TAKESHIMA KENICHI ,  SONOBE TOSHIO

IPC: G01N17/00 ,  B23K1/00 ,  B23K101/42 ,  H05K3/34

CPC classification number: Y02P70/613

Abstract: PROBLEM TO BE SOLVED: To provide a method estimating the life of solder capable of estimating the life of the solder with high precision regardless of the size or test condition of an electronic component. SOLUTION: A mounting structure wherein the electronic component is mounted by soldering is prepared and a cold heat cycle test is performed as an actual machine test to respectively calculate crack occurring life, the crack developing speed advancing in the component width direction (component short direction) of the electronic component. Further, the elastoplastic creep strain amplitude of the mounting structure is calculated by finite-element method analysis. Then, crack producing life is formulated from the strain amplitude and the crack producing life (an estimate formula of crack producing life) while the crack developing life is formulated in the width direction and long axis direction of the electronic component from the strain amplitude and the crack developing speed (first and second crack developing life estimate formulae). Thereafter, the crack producing life and the first and second crack developing lives are respectively added to calculate the life of solder. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种估计焊料寿命的方法，其能够高精度地估计焊料的寿命，而与电子部件的尺寸或测试条件无关。 解决方案：准备通过焊接安装电子部件的安装结构，并且进行冷热循环试验作为实际机器试验，以分别计算裂纹发生寿命，在部件宽度方向上前进的裂纹展开速度（部件 短路方向）。 此外，通过有限元方法分析计算了安装结构的弹塑性蠕变应变振幅。 然后，从应变振幅和应变幅度的电子部件的宽度方向和长轴方向构成裂纹发展寿命，根据应变幅度和裂纹产生寿命（裂纹产生寿命的估计公式）来制定裂纹产生寿命 破裂开发速度（第一和第二裂纹开发寿命估计公式）。 此后，分别加入裂纹产生寿命和第一次和第二次裂纹发育寿命来计算焊料的寿命。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2003234595A

公开(公告)日：2003-08-22

申请号：JP2003031505

申请日：2003-02-07

Applicant: DENSO CORP

Inventor： IMAI MASATO ,  KITAO NORIO ,  MIZUNO NAOHITO ,  NAGASAKA TAKASHI ,  SONOBE TOSHIO ,  KANAMARU KENJI

IPC: H05K9/00 ,  H01L23/00 ,  H01L25/00 ,  H05K3/46

Abstract: PROBLEM TO BE SOLVED: To provide an electromagnetic wave shielded type semiconductor device which can reduce electromagnetic noise and surge noise, while constitution and process are simple and automation is facilitated. SOLUTION: A multilayer capacitor 6, which is formed on a wiring board 2 and constituted of ground electrode layers 32, 33, 35, 36, dielectric layers 41, 42 and signal electrode layers 34, is connected with a part located between a ground line and an input signal line or an output signal line. A semiconductor chip 1 is almost surrounded and covered by the ground electrode layers 33, 35, 36 and a metal cap 4. Electromagnetic noise and surge noise, superposed on the input signal line or the output signal line of the electromagnetic wave shielded type semiconductor device or wirings in the semiconductor device which are connected with the signal lines can be reduced by the multilayer capacitor 6. The ground electrode layers 32, 33, 35, 36 cover the semiconductor chip 1 together with the metal cap 4, so that incident electromagnetic noise can be reduced. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001035882A

公开(公告)日：2001-02-09

申请号：JP36646199

申请日：1999-12-24

Applicant: DENSO CORP

Inventor： SONOBE TOSHIO ,  OGISO HOMARE ,  FUJII JUNPEI ,  SAITO ATSUSHI

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To prevent deterioration of productivity, a thermal effect on another loaded component, generation of a void in a resin and unrepairable manufacturing drawback of a BGA/CSP(ball grid array or chip size package) in a mounting structure in which an electronic component is mounted on a substrate via a solder bump. SOLUTION: A resin sheet 5 obtained by sandwiching both sides of a cured thermosetting resin plate 51 with a pair of thermosetting resin films 52 is previously prepared, and the resin sheet 5 is interposed between a BGA/CSP 2 and a substrate 3. At the same time, reflowing and curing of a solder bump 1 are performed with the solder bump 1 brought into contact with a land portion 4. Subsequently, by heating and pressurizing the solder bump 1 at a lower temperature than the melting temperature of the solder bump 1, the solder bump 1 is crushed and each of both the thermosetting resin films 52 is bonded to the BGA/CSP 2 and the substrate 3.

公开(公告)号：JP2008243998A

公开(公告)日：2008-10-09

申请号：JP2007080007

申请日：2007-03-26

Applicant: Denso Corp ,  株式会社デンソー

Inventor： TAKESHIMA KENICHI ,  KAMIMURA ATSUSHI ,  SONOBE TOSHIO

IPC: H05K3/22 ,  H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide the method of reforming the curvature of a printed-circuit board, in which the curvature of the printed-circuit board on one surface of which components are mounted by reflow soldering can be certainly reformed by use of a new structure.
SOLUTION: A printed-circuit board 50, on one surface of which components 51 are mounted by reflow soldering is placed on a heating block 10, which has a suction function and the upper surface 11 of which is flat, with the component mounting surface of the board set as an upper surface. The printed-circuit board 50 is heated to a temperature exceeding the glass transition point temperature of the resin of the printed-circuit board 50. In a state in which the heating is continued, the printed-circuit board 50 is, with the component mounting surface of the printed-circuit board 50 covered with an air leak preventing flexible material 20 having heat resistance, suctioned from its lower surface, and is thereby planarized and held. When the heating is stopped and the temperature decreases to be lower than the glass transition point temperature, the suctioning from the lower surface of the printed-circuit board 50 is released.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供重整印刷电路板的曲率的方法，其中通过回流焊接安装组件的一个表面上的印刷电路板的曲率可以通过使用来确定地改变 的新结构。 解决方案：印刷电路板50在其一个表面上通过回流焊将部件51安装在加热块10上，加热块10具有吸附功能，其上表面11是平的，部件 板的安装表面设置为上表面。 将印刷电路板50加热到超过印刷电路板50的树脂的玻璃化转变点温度的温度。在继续加热的状态下，印刷电路板50与元件安装 印刷电路板50的表面被具有耐热性的防漏气柔性材料20覆盖，从其下表面吸出，由此被平坦化和保持。 当加热停止并且温度降低到低于玻璃化转变点温度时，从印刷电路板50的下表面的抽吸被释放。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2001007503A

公开(公告)日：2001-01-12

申请号：JP17692499

申请日：1999-06-23

Applicant: DENSO CORP

Inventor： HIRAMATSU TOMOYUKI ,  OGISO HOMARE ,  SONOBE TOSHIO

IPC: H05K3/34 ,  H01L21/60

Abstract: PROBLEM TO BE SOLVED: To provide a mounting method for a BGA(ball grid array) by junctioning via mutual electrodes on a printed circuit board and in which a life against thermal fatigue is effectively improved while the crushing of melted solder is suppressed. SOLUTION: In this mounting method, solder paste 50 is printed on electrodes 21 on a whole surface of a printed circuit board 20, thermosetting resin 41 is applied at the center excepting the electrode area. After that, a BGA 10 having a solder ball 14 on a surface is so mounted on the surface of the printed circuit board 20 as the electrodes 11 and 21 to contact via each solder 14 and 50. At the next process, the solder is melted, additionally the thermosetting resin is so semi-cured as displacement correction of the BGA 10 corresponding to the printed circuit board 20 and crushing suppression of the solder in the heightwise direction to be possible and coagulation of the solder and curing of the thermosetting resin 41 are subsequently performed.

公开(公告)号：JPH11163510A

公开(公告)日：1999-06-18

申请号：JP33196697

申请日：1997-12-02

Applicant: DENSO CORP

Inventor： KAMIYA KIYOSHI ,  SONOBE TOSHIO

IPC: H05K3/34

Abstract: PROBLEM TO BE SOLVED: To provide a spacer allocated between an electronic component and a mounting substrate, wherein, being low cost, its height is assured with ease, while a distortion between the electronic component and the mounting substrate is hard to be induced and thermal fatigue of a solder is improved. SOLUTION: Between a chip part and a printed board 1, a resin member 7 of an epoxy resin comprising silica filler is provided. Thus, height of a solder 4 is assured. Since such resin member 7 as this is small in thermal expansion factor, the distortion between the chip part 2 and the printed board 1 is hard to be caused even under thermal expansion. Further, since the thermal expansion factor of the resin member 7 is small, it is close to that of the solder 4, so the thermal expansion of the resin member 7 is close to that of the solder 4, and effect on the solder 4 is less even when the resin member 7 thermally so expands as to enlarge the interval between the chip part 2 and the printed board 1. Thus, a thermal fatigue life of the solder is improved.

公开(公告)号：JP2001024030A

公开(公告)日：2001-01-26

申请号：JP19229499

申请日：1999-07-06

Applicant: DENSO CORP

Inventor： HIRAMATSU TOMOYUKI ,  SONOBE TOSHIO

IPC: H01L21/60

Abstract: PROBLEM TO BE SOLVED: To enable simultation for the shape of solder in the fused condition in the course of the manufacturing steps by obtaining the relationship between a shape of fused solder and a load to be applied to the solder bump in the fused condition. SOLUTION: A solder volume V of a solder bump 21, an interposer aperture diameter (rb) in the CSP(chip size package) side which is a radius of the interposer aperture 18a, an interposer aperture height (hb) in the CSP side which is the height in the interposer aperture 18a, a solder resist aperture (rp) in the substrate side which is the radius of the solder resist aperture 13a, and a solder resist aperture height (hp) in the substrate side which is the height in the solder resist aperture 13a are inputted to a computer. As a result, a relationship between the shape of fused solder and a load applied to the solder bump 21 in the fused condition can be obtained, based on such design factors inputted.