公开(公告)号：US08013663B2

公开(公告)日：2011-09-06

申请号：US11365772

申请日：2006-03-01

申请人： Won Jung Cho

发明人： Won Jung Cho

IPC分类号： G05F1/10

CPC分类号： H05B33/0812 ,  H05B33/0842

摘要： In one embodiment, a method is provided for preventing reverse input current from flowing into a power source. The method includes: providing a system having a plurality of operating modes for driving a load, wherein in each operating mode the power delivered to the load is a multiple of the power output from the power source; transitioning the system from one operating mode into another operating mode under predetermined conditions; if the power delivered to the load is greater than the power delivered to the power source, delaying the transition of the system from the one operating mode into the other operating mode

摘要翻译： 在一个实施例中，提供了一种用于防止反向输入电流流入电源的方法。 该方法包括：提供具有用于驱动负载的多个操作模式的系统，其中在每个操作模式中，传送到负载的功率是从电源输出的功率的倍数; 在预定条件下将系统从一个操作模式转换到另一个操作模式; 如果传递到负载的功率大于传送到电源的功率，则延迟系统从一种操作模式转换到另一操作模式

公开(公告)号：US07903106B2

公开(公告)日：2011-03-08

申请号：US11316118

申请日：2005-12-21

申请人： Ing-Jye Lan

发明人： Ing-Jye Lan

IPC分类号： G09G5/00

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0673

摘要： In one aspect, a system provides gamma correction in a thin-film-transistor (TFT) liquid-crystal-display (LCD). The system includes a digital-to-analog converter operable to receive digital control data. The digital-to-analog converter is operable to provide an output voltage for gamma correction in response to the digital control data.

摘要翻译： 在一个方面，系统在薄膜晶体管（TFT）液晶显示器（LCD）中提供伽马校正。 该系统包括可操作以接收数字控制数据的数模转换器。 数模转换器可操作以响应于数字控制数据提供用于伽马校正的输出电压。

公开(公告)号：US6134285A

公开(公告)日：2000-10-17

申请号：US864629

申请日：1997-05-28

申请人： Wei-Chi Lo

发明人： Wei-Chi Lo

IPC分类号： G06F1/04 ,  G06F7/68 ,  H04L7/02 ,  H04L7/08

CPC分类号： G06F7/68 ,  G06F1/04 ,  H04L7/02 ,  H04L7/08

摘要： In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register. In some embodiments of the data receiver an integer error compensation circuit compensates for the difference between the actual number of clock periods in a data period and the integer clock period count. A divider divides the integer clock period count to calculate an integer N and causes a data register to capture a data word on the N-th occurrence of an active edge of the clock signal after the beginning of the data word.

公开(公告)号：US08183824B2

公开(公告)日：2012-05-22

申请号：US11151163

申请日：2005-06-10

申请人： Necdet Emek ,  Mario Chunhwa Huang

发明人： Necdet Emek ,  Mario Chunhwa Huang

IPC分类号： H02J7/00

CPC分类号： H05B33/0827 ,  H05B33/0815

摘要： In one embodiment of the present invention, a system includes a power stage component operable to generate an output voltage from a power source and to provide the output voltage to an electrical device. The power stage component is capable of operating in a plurality of modes depending on a level of the power source. An adaptive mode change component, coupled to the power stage, is operable to track at least one variation which affects the voltage across the electrical device and to generate at least one control signal for changing among the plurality of operating modes of the power stage component in response to the tracking.

摘要翻译： 在本发明的一个实施例中，系统包括功率级组件，其可操作以从电源产生输出电压并向电气设备提供输出电压。 功率级组件能够根据电源的电平以多种模式操作。 耦合到功率级的自适应模式改变组件可操作以跟踪影响电气设备两端的电压的至少一个变化，并产生用于在功率级组件的多个操作模式之间改变的至少一个控制信号 回应跟踪。

公开(公告)号：US08564272B2

公开(公告)日：2013-10-22

申请号：US12006598

申请日：2008-01-04

申请人： Ding Hsu Yen ,  Wei Zhang ,  Henry H. Yuan

发明人： Ding Hsu Yen ,  Wei Zhang ,  Henry H. Yuan

IPC分类号： G05F1/575

CPC分类号： H02M1/36 ,  H02M1/32 ,  H02M3/156

摘要： Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.

公开(公告)号：US07043657B1

公开(公告)日：2006-05-09

申请号：US10682741

申请日：2003-10-08

申请人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

发明人： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

公开(公告)号：US06993600B1

公开(公告)日：2006-01-31

申请号：US10431997

申请日：2003-05-07

申请人： Dam Thanh Vo ,  Christopher Dinh ,  Pengwei Liu

发明人： Dam Thanh Vo ,  Christopher Dinh ,  Pengwei Liu

IPC分类号： G06F3/00 ,  G11C7/00

CPC分类号： G11B20/10

摘要： A controller for a writable optical media is presented. The controller includes a write control sequencer that monitors the transmission of data from a host device to the writable optical media without continuous supervision from a microcomputer. The write control sequencer monitors and controls data flow in response to descriptors which are loaded into the controller prior to the transfer by a microprocessor.

摘要翻译： 提出了一种可写光学介质的控制器。 该控制器包括一个写入控制定序器，其监视从主机设备到可写入光学介质的数据传输，而无需从微型计算机的连续监控。 写入控制定序器响应于在由微处理器传送之前加载到控制器中的描述符来监视和控制数据流。

公开(公告)号：US06937664B1

公开(公告)日：2005-08-30

申请号：US09617592

申请日：2000-07-18

申请人： Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

发明人： Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

IPC分类号： H04L25/49 ,  H04L27/00

CPC分类号： H04L25/49

摘要： An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

摘要翻译： 一种用于提供多符号信令的装置包括多符号编码器电路。 多符号编码器电路可操作以将数据编码为多个符号，每个符号由载波信号中的信号转换和信号区域唯一地定义。 耦合到多符号编码器电路的驱动器电路可操作以驱动载波信号。

公开(公告)号：US6076132A

公开(公告)日：2000-06-13

申请号：US864950

申请日：1997-05-28

申请人： Jawji Chen

发明人： Jawji Chen

IPC分类号： G06F13/364 ,  G06F13/14

CPC分类号： G06F13/364

摘要： In accordance with this invention, an arbitration unit controls access to a shared device between a plurality devices. The arbitration unit grants access to the shared device so that both the maximum latency requirement and the minimum access requirement of the devices are satisfied. In one embodiment, a first device with high access requirements uses the precedence of a second device when the second device has a higher precedence than the first device and the second device does not request access to the shared device. Thus the first device can receive access to the shared device based on the precedence of the second device or the precedence of the first device. In another embodiment, the devices are circularly ordered to determine the precedence of each device. In accordance with circular arbitration, after the first device receives access to the shared device based on the precedence of the second device, the second device is assigned the lowest precedence. Furthermore, some embodiments arrange the devices in a hierarchy of different groups. A first group within a second group is treated as a single device of the second group. One implementation of the arbitration unit includes a group pointer for each group and a precedence decoder.

摘要翻译： 根据本发明，仲裁单元控制对多个设备之间的共享设备的访问。 仲裁单元允许对共享设备的访问，使得满足设备的最大等待时间要求和最小访问要求。 在一个实施例中，当第二设备的优先级高于第一设备并且第二设备不请求访问共享设备时，具有高访问需求的第一设备使用第二设备的优先级。 因此，第一设备可以基于第二设备的优先级或第一设备的优先级来接收对共享设备的访问。 在另一个实施例中，设备被循环排序以确定每个设备的优先级。 根据循环仲裁，在第一设备基于第二设备的优先级接收到共享设备的访问之后，向第二设备分配最低优先级。 此外，一些实施例将设备排列在不同组的层级中。 第二组中的第一组被视为第二组的单个设备。 仲裁单元的一个实现包括每个组的组指针和优先解码器。

公开(公告)号：US20070139328A1

公开(公告)日：2007-06-21

申请号：US11316118

申请日：2005-12-21

申请人： Ing-Jye Lan

发明人： Ing-Jye Lan

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0673

摘要： In one aspect, a system provides gamma correction in a thin-film-transistor (TFT) liquid-crystal-display (LCD). The system includes a resistor network comprising a plurality of resistors coupled in series between a first terminal and a second terminal. The resistor network is operable to provide a plurality of voltage values. A plurality of multiplexers are coupled to the resistor network. Each multiplexer is operable to receive and multiplex the plurality of voltage values from the resistor network to provide a first rail voltage and a second rail voltage. A digital-to-analog converter, coupled to the plurality of multiplexers, is operable to receive digital control data. The digital-to-analog converter is operable to provide an output voltage for gamma correction in response to the digital control data. The output voltage has a value between the first rail voltage and the second rail voltage. In another aspect, a digital-to-analog converter with n bits of digital control provides gamma correction in a thin-film-transistor (TFT) liquid-crystal-display (LCD). The converter includes n number of switches, each of the n switches being controlled by a respective bit of digital control. A first of the n switches is one size and each of the remaining n switches is an increasingly larger size relative to the first of the n switches

摘要翻译： 在一个方面，系统在薄膜晶体管（TFT）液晶显示器（LCD）中提供伽马校正。 该系统包括电阻网络，其包括串联耦合在第一端子和第二端子之间的多个电阻器。 电阻网络可操作以提供多个电压值。 多个多路复用器耦合到电阻网络。 每个多路复用器可操作以从电阻器网络接收和复用多个电压值，以提供第一轨道电压和第二轨道电压。 耦合到多个多路复用器的数模转换器可操作以接收数字控制数据。 数模转换器可操作以响应于数字控制数据提供用于伽马校正的输出电压。 输出电压具有在第一导轨电压和第二导轨电压之间的值。 在另一方面，具有n位数字控制的数模转换器在薄膜晶体管（TFT）液晶显示器（LCD）中提供伽马校正。 该转换器包括n个开关，n个开关中的每一个由相应的数字控制位控制。 n个开关中的第一个是一个尺寸，并且剩余的n个开关中的每一个相对于n个开关中的第一个开关的尺寸越来越大