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    Two bits per cell non-volatile memory architecture
    1.
    发明授权
    Two bits per cell non-volatile memory architecture 失效
    每个单元两位非易失性存储器架构

    公开(公告)号：US08081521B2

    公开(公告)日：2011-12-20

    申请号：US12370718

    申请日：2009-02-13

    申请人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    发明人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    IPC分类号： G11C7/00

    CPC分类号： G11C16/0441

    摘要： A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

    摘要翻译： 用于保存单个二进制值的存储器电路。 第一位单元保持逻辑高值和逻辑低值中的一个，并且第二位单元也保持逻辑高值和逻辑低值中的一个。 提供电路，用于当存储器电路中的二进制值为逻辑高值时，将逻辑高值放置在第一位单元中，并且提供电路用于当第二位单元中的二进制值 存储器电路将成为逻辑低电平值。 以这种方式，存储器电路内存在逻辑高值，存储器电路内的单个二进制值是逻辑高值还是逻辑低值。 二进制值的两个值之间的差异是两个位单元中哪一个保持逻辑高值。 因此，可以在不使用读出放大器的情况下感测该存储器电路。

    Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion
    2.
    发明授权
    Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion 失效
    高级输入/输出接口，用于集成电路设备，采用二级到多级信号转换

    公开(公告)号：US06324602B1

    公开(公告)日：2001-11-27

    申请号：US09135986

    申请日：1998-08-17

    申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

    发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

    IPC分类号： G06F1338

    CPC分类号： H03M7/30 ,  G11C7/1006 ,  G11C11/56 ,  H03M5/02

    摘要： An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

    摘要翻译： 为具有可通过两级协议格式化的信号访问的存储器存储阵列的集成电路存储器提供高级输入/输出接口。 高级输入/输出接口包括一个位压缩电路，用于接收以两电平协议格式化并在集成电路存储器内产生的第一组多个信号。 比特压缩电路将第一多个两级协议信号转换成以多级协议格式化的第一信号。 一个解压缩电路接收以多级协议格式化的第二信号。 比特解压缩电路将第二多级协议信号转换为以两级协议格式化的第二多个信号。 在一个实施例中，高级输入/输出接口允许高速/带宽存储器访问，同时减少了操作所需的引脚数和操作频率。

    Arbitration method and circuit to increase access without increasing latency
    3.
    发明授权
    Arbitration method and circuit to increase access without increasing latency 失效
    仲裁方法和电路增加访问而不增加延迟

    公开(公告)号：US6076132A

    公开(公告)日：2000-06-13

    申请号：US864950

    申请日：1997-05-28

    申请人： Jawji Chen

    发明人： Jawji Chen

    IPC分类号： G06F13/364 ,  G06F13/14

    CPC分类号： G06F13/364

    摘要： In accordance with this invention, an arbitration unit controls access to a shared device between a plurality devices. The arbitration unit grants access to the shared device so that both the maximum latency requirement and the minimum access requirement of the devices are satisfied. In one embodiment, a first device with high access requirements uses the precedence of a second device when the second device has a higher precedence than the first device and the second device does not request access to the shared device. Thus the first device can receive access to the shared device based on the precedence of the second device or the precedence of the first device. In another embodiment, the devices are circularly ordered to determine the precedence of each device. In accordance with circular arbitration, after the first device receives access to the shared device based on the precedence of the second device, the second device is assigned the lowest precedence. Furthermore, some embodiments arrange the devices in a hierarchy of different groups. A first group within a second group is treated as a single device of the second group. One implementation of the arbitration unit includes a group pointer for each group and a precedence decoder.

    摘要翻译： 根据本发明，仲裁单元控制对多个设备之间的共享设备的访问。 仲裁单元允许对共享设备的访问，使得满足设备的最大等待时间要求和最小访问要求。 在一个实施例中，当第二设备的优先级高于第一设备并且第二设备不请求访问共享设备时，具有高访问需求的第一设备使用第二设备的优先级。 因此，第一设备可以基于第二设备的优先级或第一设备的优先级来接收对共享设备的访问。 在另一个实施例中，设备被循环排序以确定每个设备的优先级。 根据循环仲裁，在第一设备基于第二设备的优先级接收到共享设备的访问之后，向第二设备分配最低优先级。 此外，一些实施例将设备排列在不同组的层级中。 第二组中的第一组被视为第二组的单个设备。 仲裁单元的一个实现包括每个组的组指针和优先解码器。

    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
    4.
    发明授权
    System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream 失效
    用于半导体芯片的I / O接口的系统利用在第一数据流中向每个数据元素添加参考元素并解释以恢复第二数据流的数据元素

    公开(公告)号：US06477592B1

    公开(公告)日：2002-11-05

    申请号：US09369636

    申请日：1999-08-06

    申请人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    发明人： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

    IPC分类号： G06F1320

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

    摘要： An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

    摘要翻译： I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。

    Pseudo dual-port DRAM for simultaneous read/write access
    5.
    发明授权
    Pseudo dual-port DRAM for simultaneous read/write access 失效
    伪双端口DRAM，用于同时读/写访问

    公开(公告)号：US06259634B1

    公开(公告)日：2001-07-10

    申请号：US09576105

    申请日：2000-05-22

    申请人： Subramani Kengeri ,  Jawji Chen

    发明人： Subramani Kengeri ,  Jawji Chen

    IPC分类号： G11C700

    CPC分类号： G11C7/1075

    摘要： A system and/or method for simultaneous read/write access of 1-Transistor (1-T) dynamic random access memory (DRAM), which does not rely on a dual-port DRAM to perform read and write accesses within single clock cycle. A single-port 1-T DRAM works with modified design of read sense amplifier to perform both read and write accesses within single clock cycle, thereby retaining high performance and compact size that characterize the 1-T DRAM while allowing simultaneous read/write access that characterizes dual-port memory. Hence, single-port 1-T DRAM constitutes a pseudo dual-port 1-T DRAM that emulates the dual-port DRAM's ability in performing simultaneous read/write memory access of 1-T DRAM.

    摘要翻译： 用于同时读/写存取1晶体管（1-T）动态随机存取存储器（DRAM）的系统和/或方法，其不依赖双端口DRAM在单个时钟周期内执行读和写访问。 单端口1-T DRAM具有读取读出放大器的改进设计，可在单个时钟周期内执行读取和写入访问，从而保持高性能和紧凑的尺寸，表征1-T DRAM，同时允许同时读/写访问 表征双端口内存。 因此，单端口1-T DRAM构成伪双端口1-T DRAM，其模拟双端口DRAM执行1-T DRAM的同时读/写存储器访问的能力。

    Two Bits Per Cell Non-Volatile Memory Architecture
    7.
    发明申请
    Two Bits Per Cell Non-Volatile Memory Architecture 失效
    每个单元非易失性存储器架构的两个位

    公开(公告)号：US20100208530A1

    公开(公告)日：2010-08-19

    申请号：US12370718

    申请日：2009-02-13

    申请人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    发明人： Chee T. Chua ,  Kameswara K. Rao ,  Vithal R. Rao ,  Jawji Chen ,  Da-Guang Yu ,  J. Eric Ruetz ,  Stephen Fung

    IPC分类号： G11C7/00

    CPC分类号： G11C16/0441

    摘要： A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.

    摘要翻译： 用于保存单个二进制值的存储器电路。 第一位单元保持逻辑高值和逻辑低值中的一个，并且第二位单元也保持逻辑高值和逻辑低值中的一个。 提供电路，用于当存储器电路中的二进制值为逻辑高值时，将逻辑高值放置在第一位单元中，并且提供电路用于当第二位单元中的二进制值 存储器电路将成为逻辑低电平值。 以这种方式，存储器电路内存在逻辑高值，存储器电路内的单个二进制值是逻辑高值还是逻辑低值。 二进制值的两个值之间的差异是两个位单元中哪一个保持逻辑高值。 因此，可以在不使用读出放大器的情况下感测该存储器电路。