公开(公告)号：US08391092B2

公开(公告)日：2013-03-05

申请号：US12801929

申请日：2010-07-02

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C11/4094 ,  G11C2211/4068

摘要： A method for eliminating bit line leakage current of a memory cell in random access memory devices comprises the steps of: periodically activating a pre-charge equalization circuit, which provides a pre-charge voltage to a pair of complementary bit lines of a memory cell, if the memory cell is in a self-refresh mode or a standby mode; and temporarily activating the pre-charge equalization circuit after the memory cell is refreshed if the memory cell is in the self-refresh mode or the standby mode.

摘要翻译： 一种用于消除随机存取存储器件中的存储单元的位线泄漏电流的方法包括以下步骤：周期地激活预充电均衡电路，该预充电均衡电路为存储器单元的一对互补位线提供预充电电压， 如果存储器单元处于自刷新模式或待机模式; 以及如果存储器单元处于自刷新模式或待机模式，则刷新存储器单元之后暂时激活预充电均衡电路。

公开(公告)号：US20130021855A1

公开(公告)日：2013-01-24

申请号：US13187548

申请日：2011-07-21

申请人： Chung-Zen Chen

发明人： Chung-Zen Chen

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C7/1066 ,  G11C7/1072 ,  G11C11/4096

摘要： The present invention provides a semiconductor memory device, the voltage divider circuit comprises a data line sense amplifier and an input output data sensing circuit. The data line sense amplifier receives a data line signal pair and senses the data line signal pair in a first timing period to generate a first output data and a second output data, wherein, the first output data and the second output data are complementary. The input output data sensing circuit receives at least one reference output data and one of the first and the second output data. The input output data sensing circuit generates a sensed data by comparing voltage levels of the reference output data and the one of the first and the second output data in a second timing period, wherein the voltage level of the reference output data is a pre-determined voltage level.

摘要翻译： 本发明提供了一种半导体存储器件，该分压器电路包括数据线读出放大器和输入输出数据检测电路。 数据线读出放大器接收数据线信号对，并在第一定时周期内感测数据线信号对，以产生第一输出数据和第二输出数据，其中第一输出数据和第二输出数据互补。 输入输出数据检测电路接收至少一个参考输出数据和第一和第二输出数据之一。 输入输出数据检测电路通过在第二定时周期中比较参考输出数据和第一和第二输出数据中的一个的电压电平来产生感测数据，其中参考输出数据的电压电平是预先确定的 电压电平。

公开(公告)号：US08081520B2

公开(公告)日：2011-12-20

申请号：US12699851

申请日：2010-02-03

申请人： Chung-Zen Chen

发明人： Chung-Zen Chen

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/04

摘要： An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction.

摘要翻译： 提供了一种闪存装置的过擦除校正方法。 闪存装置至少包括微处理器，存储器阵列，位线交换单元和列解码器。 通过在过擦除校正的周期期间控制闪速存储器的列解码器，列解码器将控制信号输出到位线交换单元，用于根据位线泄漏电流的大小选择至少一个位线 。 由于位线泄漏电流引起的电荷泵电压的下降减小，因此，在过擦除校正期间有效地执行过擦除校正。

公开(公告)号：US08031550B2

公开(公告)日：2011-10-04

申请号：US12132098

申请日：2008-06-03

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C5/14

CPC分类号： G11C11/406 ,  G11C5/147 ,  G11C11/4074 ,  G11C2211/4061 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.

摘要翻译： 用于存储电路的电压调节器电路包括分压器，电容器，有源模式电压调节器和待机模式电压调节器。 主动模式电压调节器在激活模式下始终处于打开状态，并且每当请求刷新时都会打开。 待机模式电压调节器在待机模式下周期性地接通，每当请求刷新时都会打开。 此外，有源稳压器使用比待机模式电压调节器使用的晶体管更强的晶体管，而有源模式电压调节器和待机模式电压调节器都耦合到分压器和电容器。

公开(公告)号：US20110228623A1

公开(公告)日：2011-09-22

申请号：US12728508

申请日：2010-03-22

申请人： CHUNG ZEN CHEN

发明人： CHUNG ZEN CHEN

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/143

摘要： A power-up circuit comprises an external supply voltage potential detector, a first internal supply voltage potential detector, a second internal supply voltage potential detector, and a logic circuit. The external supply voltage potential detector is configured to detect a supply voltage that is external to the memory device and to generate a first detection signal indicating whether a voltage potential of the external supply voltage reaches a first predetermined value. The first internal supply voltage potential detector is configured to detect a first internal supply voltage that is internal to the memory device and to generate a second detection signal indicating whether a voltage potential of the first internal supply voltage reaches a second predetermined value. The second internal supply voltage potential detector is configured to detect a second internal supply voltage that is internal to the memory device and to receive the first detection signal and an output voltage of the first internal supply voltage potential detector for generating a third detection signal indicating whether the voltage potentials of the external supply voltage and the first and second internal supply voltages reach the first, second, and third predetermined values respectively. The logic circuit is configured to receive the third detection signal and to generate a power-up signal.

摘要翻译： 上电电路包括外部电源电压检测器，第一内部电源电压检测器，第二内部电源电压电位检测器和逻辑电路。 外部电源电压检测器被配置为检测存储器件外部的电源电压并产生指示外部电源电压的电压电位是否达到第一预定值的第一检测信号。 第一内部电源电压检测器被配置为检测存储器件内部的第一内部电源电压并产生指示第一内部电源电压的电压电压是否达到第二预定值的第二检测信号。 第二内部电源电压检测器被配置为检测存储器件内部的第二内部电源电压并且接收第一内部电源电压检测器的第一检测信号和第一内部电源电压检测器的输出电压，以产生指示是否 外部电源电压和第一和第二内部电源电压的电压电位分别达到第一，第二和第三预定值。 逻辑电路被配置为接收第三检测信号并产生上电信号。

公开(公告)号：US20110170366A1

公开(公告)日：2011-07-14

申请号：US13053727

申请日：2011-03-22

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C7/04 ,  G11C8/00

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  G11C2211/4068

摘要： A method for determining a temperature in a circuit comprises receiving a periodic signal. A frequency of the periodic signal is an increasing function of temperature. A number of oscillations of the periodic signal is determined during a time interval. A length of the time interval is an increasing function of temperature. The temperature is based on the determined number of oscillations.

摘要翻译： 用于确定电路中的温度的方法包括接收周期信号。 周期信号的频率是温度的增加函数。 在时间间隔期间确定周期信号的多个振荡。 时间间隔的长度是温度的增加函数。 温度基于确定的振荡次数。

公开(公告)号：US07929366B2

公开(公告)日：2011-04-19

申请号：US12619157

申请日：2009-11-16

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4074 ,  G11C2211/4068

摘要： A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.

摘要翻译： 集成电路中的温度检测器包括温度依赖性电压发生器，环形振荡器，定时器和时钟驱动记录器。 温度依赖性电压发生器被配置为产生至少一个温度依赖电压。 环形振荡器被配置为产生受至少一个温度相关电压之一影响的时钟信号。 定时器被配置为产生受温度依赖电压之一影响的超时信号。 时钟驱动记录器具有响应于时钟信号和超时信号的时钟输入端子。

公开(公告)号：US07705631B2

公开(公告)日：2010-04-27

申请号：US12021075

申请日：2008-01-28

申请人： Chung-Zen Chen

发明人： Chung-Zen Chen

IPC分类号： H03K19/0175

CPC分类号： H03K3/356182 ,  G11C5/145 ,  G11C16/12

摘要： A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors.

摘要翻译： 电平移位器包括电压转换电路，电压上拉电路和控制信号发生电路。 电压转换电路被配置为接收第一电压电平的输入信号并输出​​第二电压电平的输出信号。 电压上拉电路耦合到电压转换电路并且被配置为响应于控制信号而将电平移位器的输出节点的电压迅速上拉到第二电压电平。 控制信号发生电路被配置为接收输入信号并且向电压上拉电路提供控制信号。 控制信号发生电路包括三个晶体管。

公开(公告)号：US07643352B2

公开(公告)日：2010-01-05

申请号：US12132153

申请日：2008-06-03

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3477

摘要： A method for erasing flash memory comprises the steps of: setting a critical ending condition; simultaneously erasing selected multiple sectors of the flash memory; stopping simultaneous erasing if one of the selected multiple sectors meets the critical ending condition; and erasing the remainder of each of the selected multiple sectors sequentially.

摘要翻译： 一种擦除闪速存储器的方法包括以下步骤：设置临界结束条件; 同时擦除闪存的所选择的多个扇区; 如果所选择的多个扇区之一满足临界结束条件，则停止同时擦除; 并且顺序地擦除所选择的多个扇区中的每一个的剩余部分。

公开(公告)号：US07606952B2

公开(公告)日：2009-10-20

申请号：US11593174

申请日：2006-11-06

申请人： Chung Zen Chen

发明人： Chung Zen Chen

IPC分类号： G06F3/00 ,  G06F1/00 ,  G06F1/04

CPC分类号： G06F13/4291 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2216/30

摘要： A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits of the data strings transmitted in a period of the first system clock signal. A second system clock signal is generated by the first system clock signal to provide a double frequency to enhance the transmission rate of all the data inputted into or outputted from the SPI serial flash.

摘要翻译： 一种用于串行外围接口（SPI）串行闪存的传输方法包括以下步骤：提供第一系统时钟信号，并且在第一系统时钟信号的周期内发送数据串的每两位发送多个数据串。 由第一系统时钟信号产生第二系统时钟信号以提供双倍频率以增强输入或输出的SPI串行闪存的所有数据的传输速率。