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    AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE
    2.
    发明申请
    AUTOMATED SPECIFICATION BASED FUNCTIONAL TEST GENERATION INFRASTRUCTURE 失效
    基于自动规范的功能测试生成基础设施

    公开(公告)号：US20090235121A1

    公开(公告)日：2009-09-17

    申请号：US12212736

    申请日：2008-09-18

    Applicant: Debaditya Mukherjee ,  Anil Raj Gopalakrishnan

    Inventor： Debaditya Mukherjee ,  Anil Raj Gopalakrishnan

    IPC: G06F11/263

    CPC classification number: G06F11/263

    Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

    Abstract translation: 一种方法，包括以下步骤：（A）生成代码，（B）将一个或多个约束构造应用于代码;（C）响应于将约束构造应用于代码而生成覆盖代码和第二代码（D ）响应于所述代码生成第三代码，以及（E）响应于所述第二代码生成一个或多个汇编语言测试。

    Self-testing circuitry for VLSI units
    4.
    发明授权
    Self-testing circuitry for VLSI units 失效
    用于VLSI单元的自检电路

    公开(公告)号：US5006787A

    公开(公告)日：1991-04-09

    申请号：US364411

    申请日：1989-06-12

    Applicant: Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee

    Inventor： Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee

    IPC: G01R31/3185 ,  G11C29/32

    CPC classification number: G01R31/318555 ,  G01R31/318544 ,  G11C29/32

    Abstract: An application specific integrated circuit is provided on a chip where a combinatorial logic circuitry such as a RAM memory array, logic circuitry and control circuitry may be operated in the normal mode with the addition of a built-in, self-test feature whereby the registers can be converted to multifunction shift registers which are connected in a serial fashion to form a shift chain snake through which data patterns can be shifted. Additionally, control circuitry is provided to select certain multifunction shift registers as test pattern generators and other multifunction shift registers are receivers of signatures which can be accessed by a maintenance controller to check proper operability of the system and its combinatorial logic.

    Abstract translation: 在芯片上提供专用集成电路，其中诸如RAM存储器阵列，逻辑电路和控制电路的组合逻辑电路可以在正常模式下操作，同时附加内置的自检特征，由此寄存器 可以转换成以串行方式连接的多功能移位寄存器，以形成可以移位数据模式的移位链蛇。 此外，提供控制电路以选择某些多功能移位寄存器作为测试模式发生器，并且其他多功能移位寄存器是可由维护控制器访问的签名的接收器，以检查系统及其组合逻辑的适当可操作性。

    Error log system for self-testing in very large scale integrated circuit (VLSI) units
    7.
    发明授权
    Error log system for self-testing in very large scale integrated circuit (VLSI) units 失效
    用于大规模集成电路（VLSI）单元自检的错误日志系统

    公开(公告)号：US4932028A

    公开(公告)日：1990-06-05

    申请号：US209664

    申请日：1988-06-21

    Applicant: Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee ,  Gary C. Whitlock

    Inventor： Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee ,  Gary C. Whitlock

    IPC: G06F11/07 ,  G06F11/32

    CPC classification number: G06F11/0772 ,  G06F11/32

    Abstract: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

    Abstract translation: VSLI芯片采用寄存器实现，该寄存器记录由并发错误检测电路（CED）感测到的芯片内发生的永久性和间歇性错误。 如果检测到致命错误（将破坏芯片操作的可靠性），则芯片被固定为保持模式（冻结）。 信号通知给协调维护控制器的中断可以将错误信息传递给外部计算机进行显示和定位故障区域。

    Automated specification based functional test generation infrastructure
    9.
    发明授权
    Automated specification based functional test generation infrastructure 失效
    基于自动规范的功能测试生成基础设施

    公开(公告)号：US08230263B2

    公开(公告)日：2012-07-24

    申请号：US12212736

    申请日：2008-09-18

    Applicant: Debaditya Mukherjee ,  Anil Raj Gopalakrishnan

    Inventor： Debaditya Mukherjee ,  Anil Raj Gopalakrishnan

    IPC: G06F11/00 ,  G06F17/50

    CPC classification number: G06F11/263

    Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

    Abstract translation: 一种方法，包括以下步骤：（A）生成代码，（B）将一个或多个约束构造应用于代码;（C）响应于将约束构造应用于代码而生成覆盖代码和第二代码（D ）响应于所述代码生成第三代码，以及（E）响应于所述第二代码生成一个或多个汇编语言测试。

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