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公开(公告)号：US20250037780A1
公开(公告)日：2025-01-30
申请号：US18534727
申请日：2023-12-11
Applicant: Faraday Technology Corp.
Inventor： Chi-Chou Huang , Yun-Chuan Teng , Yu-Tang Wang
IPC: G11C29/12
Abstract: The disclosure provides an electronic fuse (eFuse) device and an operation method thereof. The eFuse device includes an eFuse, a readout circuit, a register, and a safety control device. The readout circuit reads out target data recorded by the eFuse to the register and the safety control device. The safety control device compares the target data provided by the readout circuit with the target data provided by the register to determine whether a soft error occurs in the target data stored in the register. When the soft error occurs in the target data stored in the register, the readout circuit reads out the target data recorded by the eFuse again to the register and the safety control device.
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公开(公告)号：US20240304268A1
公开(公告)日：2024-09-12
申请号：US18540879
申请日：2023-12-15
Applicant: Faraday Technology Corp.
Inventor： Chih-Hung Wu , Ko-Ching Chao , Po-Wen Hsiao , Zhou-Lun Liou
CPC classification number: G11C29/028 , G11C7/14 , G11C8/18
Abstract: A method and apparatus for performing self-calibration of receiver offset without shorting differential input terminals of a receiver are provided. The self-calibration includes: inputting input signals carrying predetermined data patterns into a plurality of receivers; performing data eye width measurement on the input signals received by the plurality of receivers to obtain multiple first data eye widths and multiple second data eye widths respectively corresponding to first and second data bytes; performing first offset calibration to make the multiple first data eye widths converge to a first common data eye width; performing second offset calibration to make the multiple second data eye widths be equal to the multiple first data eye widths, respectively, and converge to the first common data eye width; and performing reference voltage calibration on a reference voltage to optimize the multiple first data eye widths and the multiple second data eye widths.
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3.发明公开公开(公告)号：US20240192714A1
公开(公告)日：2024-06-13
申请号：US18079837
申请日：2022-12-12
Applicant: Faraday Technology Corp.
Inventor： Sivaramakrishnan Subramanian , Hussainvali Shaik , Eswar Reddi
Abstract: A voltage regulator provides a regulated voltage to a double data rate (DDR) Physical Interface (PHY) including a plurality of delay elements. The voltage regulator includes: an amplifier, for receiving a voltage at a first input terminal and generating an output voltage; a first MOSFET coupled to a supply voltage and a second input terminal of the amplifier; a second MOSFET coupled in parallel with the first MOSFET for generating a first current in response to a first enable signal; a load, coupled to the first MOSFET and the second MOSFET, for generating the regulated voltage; and a load capacitor, coupled in parallel with the load. The first enable signal is generated by inputting a gate enable signal for a delay element of the plurality of delay elements into a delay circuit corresponding to the delay element.
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公开(公告)号：US11949423B2
公开(公告)日：2024-04-02
申请号：US17846018
申请日：2022-06-22
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain , Prateek Kumar Goyal
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/099 , H04L7/0016
Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.
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公开(公告)号：US20240072814A1
公开(公告)日：2024-02-29
申请号：US17893191
申请日：2022-08-23
Applicant: Faraday Technology Corp.
Inventor： VINOD KUMAR JAIN
CPC classification number: H03L7/1976 , H03L7/0891 , H03L7/099
Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.
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Patent Agency Ranking
公开(公告)号：US20230421158A1
公开(公告)日：2023-12-28
申请号：US17846018
申请日：2022-06-22
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain , Prateek Kumar Goyal
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/099 , H04L7/0016
Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.
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7.发明公开公开(公告)号：US20230253028A1
公开(公告)日：2023-08-10
申请号：US17667499
申请日：2022-02-08
Applicant: Faraday Technology Corp.
Inventor： Sridhar Cheruku , Sivaramakrishnan Subramanian , Hussainvali Shaik , Ko-Ching Chao
IPC: G11C11/4076
CPC classification number: G11C11/4076
Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins
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公开(公告)号：US11582018B2
公开(公告)日：2023-02-14
申请号：US17394299
申请日：2021-08-04
Applicant: Faraday Technology Corp.
Inventor： Jing-Zhi Gao , Yu-Hsin Tseng , Yung-Sung Chang , Zhi-Xin Lin
IPC: H04L7/00
Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.
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公开(公告)号：US20220337385A1
公开(公告)日：2022-10-20
申请号：US17394299
申请日：2021-08-04
Applicant: Faraday Technology Corp.
Inventor： Jing-Zhi Gao , Yu-Hsin Tseng , Yung-Sung Chang , Zhi-Xin Lin
IPC: H04L7/00
Abstract: A clock data calibration circuit including a first comparator, a multi-phase clock generator, a plurality of samplers, a plurality of data comparators and a data selector is provided. The first comparator compares first input data with second input data to generate a data signal. The multi-phase clock generator generates a plurality of clock signals, and the clock signals are divided into a plurality of clock groups. The sampler samples the data signal according to the clock groups to respectively generate a plurality of first sampled data signal groups. The data comparators respectively sample the first sampled data signal groups according to selected clocks to generate a plurality of second sampled data signal groups. Each data comparator generates a plurality of status flags according to a variation state of a plurality of second sampled data. The data selector generates a plurality of output data signals according to the status flags.
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10.发明申请公开(公告)号：US20210313970A1
公开(公告)日：2021-10-07
申请号：US17178194
申请日：2021-02-17
Applicant: FARADAY TECHNOLOGY CORPORATION , Faraday Technology Corp.
Inventor： LING CHEN , Andrew Chao , XIAO-DONG FEI
IPC: H03K3/012 , H03K5/01 , H03K5/1252 , H03K3/037 , H04B1/16
Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.
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