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公开(公告)号：US11949423B2
公开(公告)日：2024-04-02
申请号：US17846018
申请日：2022-06-22
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain , Prateek Kumar Goyal
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/099 , H04L7/0016
Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.
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Patent Agency Ranking
公开(公告)号：US20230421158A1
公开(公告)日：2023-12-28
申请号：US17846018
申请日：2022-06-22
Applicant: Faraday Technology Corp.
Inventor： Mikhail Tamrazyan , Vinod Kumar Jain , Prateek Kumar Goyal
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/099 , H04L7/0016
Abstract: A clock and data recovery device that includes a first phase detector, a pulse filter, a charge pump, a loop filter and a voltage-controlled oscillator is introduced. The first phase detector generates a first phase state signal according to a data signal and a first output signal. The pulse filter adjusts the first phase state signal according to a capacitance of a loop capacitor to generate a filtered signal. The charge pump generates a pumping signal according to the filtered signal. The loop filter generates a control signal according to the pumping signal. The voltage-controlled oscillator generates a second output signal and adjust a frequency of the second output signal according to the control signal, wherein the first output signal is generated according to the second output signal.
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公开(公告)号：US20250023559A1
公开(公告)日：2025-01-16
申请号：US18351513
申请日：2023-07-13
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain , Mikhail Tamrazyan
Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.
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公开(公告)号：US11831287B2
公开(公告)日：2023-11-28
申请号：US17531811
申请日：2021-11-22
Applicant: Faraday Technology Corp.
Inventor： Prateek Kumar Goyal , Raghu Nandan Chepuri , Vinod Kumar Jain
CPC classification number: H03G3/3084 , H03F3/45 , H03M1/12 , H04B10/6933 , H03F2200/375 , H03F2203/45212
Abstract: A method for removing offset in a receiver of an integrated circuit (IC) includes: determining digital codes of differential input voltages of an amplifier in a first receiving lane of the receiver; comparing the digital codes to a digital code corresponding to an optimum common mode voltage (VCM) of the receiver; according to the comparison, determining a bias code for adjusting both the differential input voltages to match the optimum VCM; and inputting the bias code to a bias circuit of the receiver. The first receiving lane of the receiver includes a plurality of amplifiers. The method steps are repeated for each amplifier of the plurality of amplifiers, and then repeated for all receiving lanes of the IC.
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公开(公告)号：US12244317B2
公开(公告)日：2025-03-04
申请号：US18351513
申请日：2023-07-13
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain , Mikhail Tamrazyan
Abstract: A conversion circuit includes a replica feedback loop circuit and a CML to CMOS converter. The replica feedback loop circuit of a conversion circuit includes a first inverter, a first-stage amplifier and a second-stage amplifier. An input terminal of the first inverter is shorted to an output terminal of the first inverter. The second-stage amplifier of the replica feedback loop circuit is a replica of a half of a differential amplifier of the CML to CMOS converter. The replica feedback loop circuit is configured to generate a bias voltage that is used to bias the differential amplifier of the CML to CMOS converter, such that a common mode (CM) voltage outputted by the differential amplifier is same as a switching threshold voltage of a second inverter of the CML to CMOS converter.
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公开(公告)号：US11909409B1
公开(公告)日：2024-02-20
申请号：US17893191
申请日：2022-08-23
Applicant: Faraday Technology Corp.
Inventor： Vinod Kumar Jain
CPC classification number: H03L7/1976 , H03L7/0891 , H03L7/099
Abstract: A Phase Locked Loop (PLL) with reduced jitter includes: a phase detector, for comparing the phases of a reference clock and feedback clock to generate up and down control signals; a Voltage Controlled Oscillator (VCO) for generating an oscillation signal; an output divider, for dividing the oscillation signal to generate an output clock; a fractional feedback divider for receiving the oscillation signal and performing frequency division on the oscillation signal according to a modulated sequence to generate a modulated clock; and a divider coupled in series to the fractional feedback divider, for dividing the modulated clock of the fractional feedback divider by a fixed modulus to generate a divided clock. A frequency of the modulated clock of the fractional feedback divider is an integer multiple of the frequency of the divided clock, and one of the modulated clock and divided clock is used as the feedback clock.
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