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    Reconfigurable state machine
    1.
    发明授权
    Reconfigurable state machine 有权
    可重构状态机

    公开(公告)号：US07353347B2

    公开(公告)日：2008-04-01

    申请号：US10947877

    申请日：2004-09-23

    申请人： Fuk Ho Pius Ng ,  Y. Paul Chiang

    发明人： Fuk Ho Pius Ng ,  Y. Paul Chiang

    IPC分类号： G06F12/00 ,  G06F7/38 ,  G11C15/00

    CPC分类号： G11C15/00

    摘要： A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

    摘要翻译： 提供可重构状态机。 状态机包括用于存储当前状态的当前状态寄存器和每个状态机状态的至少一个可编程状态条目。 每个可编程项目包括多个外部信号输入，当前状态标签，至少一个下一个状态条件和相应的下一个状态输出。 下一状态匹配电路将当前状态与当前状态标签进行比较，并将下一状态条件中的每一个与至少一个外部信号输入进行比较，以产生下一状态匹配输出。

    Microprocessor with functional units that can be selectively coupled
    2.
    发明授权
    Microprocessor with functional units that can be selectively coupled 失效
    具有可选择耦合的功能单元的微处理器

    公开(公告)号：US06230278B1

    公开(公告)日：2001-05-08

    申请号：US08850872

    申请日：1997-05-02

    申请人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill ,  Frank L. Laczko, Sr. ,  Dong-Seok Youm ,  David (Shiu) W. Kam

    发明人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill ,  Frank L. Laczko, Sr. ,  Dong-Seok Youm ,  David (Shiu) W. Kam

    IPC分类号： G06F128

    CPC分类号： G06F9/3879 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30018 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/355 ,  G06F9/3877 ,  Y02D10/171

    摘要： A data processing device is provided which has multiprocessors that can be configured on a cycle by cycle basis as loosely coupled or tightly coupled. Bit-stream Processing Unit (BPU) 110 executes instructions from ROM 112 and accesses data from RAM 111. Similarly, Arithmetic Unit (AU) 120 executes instructions from ROM 122 and accesses data from RAM 121. Both processor operate in parallel and exchange data by accessing RAM 121. AU 120 can receive an instruction directive from BPU 110 directing it to perform a selected sequence of instructions in a loosely coupled manner. AU 120 can also receive an instruction directive from BPU 110 directing that a portion of AU 120 operationally replace a portion of BPU 110 for the duration of one instruction which allows data to be passed directly between the processors in a tightly coupled manner.

    摘要翻译： 提供了一种数据处理装置，其具有可以以逐周期为基础配置为松散耦合或紧密耦合的多处理器。 位流处理单元（BPU）110执行来自ROM 112的指令并从RAM 111访问数据。类似地，算术单元（AU）120执行来自ROM 122的指令并从RAM 121访问数据。两个处理器并行操作并且通过 访问RAM 121.AU 120可以从BPU 110接收指令，指示它以松散耦合的方式执行选定的指令序列。 AU 120还可以接收来自BPU 110的指令，指示AU 120的一部分在一个指令的持续时间内可操作地替换BPU 110的一部分，这允许以紧密耦合的方式直接在处理器之间传递数据。

    Method and apparatus for providing fast interrupt response using a ghost instruction
    3.
    发明授权
    Method and apparatus for providing fast interrupt response using a ghost instruction 失效
    使用鬼指令提供快速中断响应的方法和装置

    公开(公告)号：US5931934A

    公开(公告)日：1999-08-03

    申请号：US850431

    申请日：1997-05-02

    申请人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng

    发明人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng

    IPC分类号： G06F9/48 ,  G06F9/46

    CPC分类号： G06F9/4812

    摘要： A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a portion of a memory 121 is used as an output buffer for holding a portion of processed data which is output by an output interface 140. A processing unit 110 within the processing device manages the flow of input and output data. The input interface asserts an I/O request 860 when it receives a data word, and the output interface asserts an I/O request 870 when it needs a data word. In response to an I/O request, fast interrupt circuitry inserts a ghost instruction which is formed by doppelganger circuitry into an instruction sequence which is being accessed from a ROM 112. The ghost instruction performs the requested data transfer.

    摘要翻译： 数据处理装置100使用随机存取存储器111的一部分作为输入缓冲器，用于保存由输入接口130接收的数据流的一部分。同样地，存储器121的一部分被用作输出缓冲器 用于保持由输出接口140输出的处理数据的一部分。处理设备内的处理单元110管理输入和输出数据的流程。 当接收到数据字时，输入接口置位I / O请求860，当输出接口需要数据字时，输出接口置位I / O请求870。 响应于I / O请求，快速中断电路将由doppelganger电路形成的重影指令插入到从ROM 112进行访问的指令序列中。幻影指令执行所请求的数据传送。

    Apparatus for Knowledge Based Evolutionary Learning in AI systems
    5.
    发明申请
    Apparatus for Knowledge Based Evolutionary Learning in AI systems 有权

    公开(公告)号：US20210365793A1

    公开(公告)日：2021-11-25

    申请号：US16880346

    申请日：2020-05-21

    申请人： Nagarjun Pogakula Surya ,  Gomathi Sankar ,  Fuk Ho Pius Ng ,  Satish Padmanabhan

    发明人： Nagarjun Pogakula Surya ,  Gomathi Sankar ,  Fuk Ho Pius Ng ,  Satish Padmanabhan

    IPC分类号： G06N3/08 ,  G06N3/04

    摘要： Systems and methods are disclosed for training a previously trained neural network with incremental dataset. Original train data is provided to a neural network and the neural network is trained based on the plurality of classes in the sets of training data and/or testing data. The connected representation and the weights of the neural network is the model of the neural network. The trained model is to be updated for an incremental train data. The embodiments provide a process by which the trained model is updated for the incremental train data. This process creates a ground truth for the original training data and trains on the combined set of original train data and the incremental train data. The incremental training is tested on a test data to conclude the training and to generate the incremental trained model, minimizing the knowledge learned with the original data. Thus, the results remain consistent with the original model trained by the original dataset except the incremental train data.

    Reconfigurable state machine
    6.
    发明申请
    Reconfigurable state machine 有权
    可重构状态机

    公开(公告)号：US20060062036A1

    公开(公告)日：2006-03-23

    申请号：US10947877

    申请日：2004-09-23

    申请人： Fuk Ho Pius Ng ,  Y. Chiang

    发明人： Fuk Ho Pius Ng ,  Y. Chiang

    IPC分类号： G11C15/00

    CPC分类号： G11C15/00

    摘要： A reconfigurable state machine is provided. The state machine includes a current state register, for storing a current state, and at least one programmable state entry per state of the state machine. Each programmable entry includes a plurality of external signal inputs, a current state tag, at least one next state condition, and a respective next state output. A next state match circuit compares the current state with the current state tag and compares each of the next state conditions with at least one of the external signal inputs to produce a next state match output.

    摘要翻译： 提供可重构状态机。 状态机包括用于存储当前状态的当前状态寄存器和每个状态机状态的至少一个可编程状态条目。 每个可编程项目包括多个外部信号输入，当前状态标签，至少一个下一个状态条件和相应的下一个状态输出。 下一状态匹配电路将当前状态与当前状态标签进行比较，并将下一状态条件中的每一个与至少一个外部信号输入进行比较，以产生下一状态匹配输出。

    Data processing device with an indexed immediate addressing mode
    7.
    发明授权
    Data processing device with an indexed immediate addressing mode 失效
    具有索引立即寻址模式的数据处理设备

    公开(公告)号：US06272615B1

    公开(公告)日：2001-08-07

    申请号：US08851573

    申请日：1997-05-02

    申请人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill

    发明人： Stephen (Hsiao Yi) Li ,  Jonathan Rowlands ,  Fuk Ho Pius Ng ,  Maria B. H. Gill

    IPC分类号： G06F1200

    CPC分类号： G06F9/355 ,  G06F9/3004 ,  G06F9/30061 ,  G06F9/30167 ,  G06F9/322 ,  G06F9/325 ,  G06F9/345 ,  G06F9/35 ,  G06F9/383

    摘要： A data processing device is provided with an indexed-immediate addressing mode for processing streams of data. An instruction register 900 receives an instruction for execution. Decoding circuitry 913 selects a register specified by a field in an instruction to provide an index value. An immediate field from the instruction is combined with the index value by multiplexor 910 to form an address which can be used to access a data value or to form a target address for a branch instruction. Mux control 915 parses the immediate value to determine how to combine the immediate value and the index value.

    摘要翻译： 数据处理设备具有用于处理数据流的索引立即寻址模式。 指令寄存器900接收执行指令。 解码电路913选择由指令中的字段指定的寄存器以提供索引值。 来自指令的立即字段与索引值通过多路复用器910组合以形成可用于访问数据值或形成分支指令的目标地址的地址。 Mux控制915解析立即值，以确定如何组合立即值和索引值。

    Boolean logic tree reduction circuit
    9.
    发明授权
    Boolean logic tree reduction circuit 失效
    布尔逻辑树缩减电路

    公开(公告)号：US07002493B2

    公开(公告)日：2006-02-21

    申请号：US10754665

    申请日：2004-01-08

    申请人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

    发明人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

    IPC分类号： H03M7/00

    CPC分类号： G06F7/00 ,  G06F17/505

    摘要： A method and apparatus are provided for performing a Boolean logic tree function on all bits of a multiple-bit binary input data word having a plurality of bit positions. Each bit has one of first and second complementary logic states. A modified data word is formed by packing all the bits of the input data word having the first logic state into a first contiguous set of bit positions in the modified data word and all the bits of the input data word having the second logic state into a second contiguous set of the bit positions in the modified data word. The number of bit positions in the first and second sets is greater than or equal to zero. A result of the Boolean logic tree function is generated based on a pattern of the first and second logic states in the modified data word.

    摘要翻译： 提供了一种用于对具有多个位位置的多位二进制输入数据字的所有位执行布尔逻辑树函数的方法和装置。 每个位具有第一和第二互补逻辑状态之一。 通过将具有第一逻辑状态的输入数据字的所有位打包到经修改的数据字中的位置的第一连续集合中，并将具有第二逻辑状态的输入数据字的所有位组合成为第 经修改的数据字中的位位置的第二连续集合。 第一组和第二组中的位位数大于或等于零。 基于修改数据字中的第一和第二逻辑状态的模式生成布尔逻辑树函数的结果。

    Shift and recode multiplier
    10.
    发明申请
    Shift and recode multiplier 审中-公开
    移位和重新编码乘数

    公开(公告)号：US20050228845A1

    公开(公告)日：2005-10-13

    申请号：US10822362

    申请日：2004-04-12

    申请人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

    发明人： Fuk Ho Pius Ng ,  Liem Thanh Nguyen

    IPC分类号： G06F7/52 ,  G06F7/53 ,  G06F7/533

    CPC分类号： G06F7/5306 ,  G06F7/5338

    摘要： A method and apparatus are provided for multiplying a multiplicand by a multiplier. The method and apparatus generate a plurality of partial products. Each partial product has a plurality of bits having respective binary weights, wherein each bit can have a first or second logic state. A first set of multiple-bit columns is formed from bits of the plurality of partial products, wherein the bits in each column of the first set have the same binary weight. Each multiple-bit column in the first set is encoded into a respective modified partial product, which represents a number of bits in the column having the first logic state. This process can be repeated until the number of partial products is reduces to a desired number.

    摘要翻译： 提供了一种用于将被乘数乘以乘数的方法和装置。 该方法和装置产生多个部分积。 每个部分乘积具有多个具有相应二进制权重的比特，其中每个比特可以具有第一或第二逻辑状态。 第一组多位列由多个部分乘积的位形成，其中第一组的每列中的位具有相同的二进制权重。 第一集合中的每个多位列被编码成相应的修改的部分乘积，其表示具有第一逻辑状态的列中的位数。 该过程可以重复，直到部分产物的数量减少到所需数量。