公开(公告)号：US06297144B1

公开(公告)日：2001-10-02

申请号：US09521085

申请日：2000-03-07

申请人： Hsin-Li Cheng ,  Chang-Da Yang ,  Ping-Wei Wang

发明人： Hsin-Li Cheng ,  Chang-Da Yang ,  Ping-Wei Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76895

摘要： The present invention discloses a novel damascene local interconnect process to avoid junction leakage caused by poor interface of the interconnection with isolation edges. The process comprises the steps of: (a) forming a first dielectric layer over the substrate surface; (b) forming an interconnection in the upper level of the dielectric layer which spans over the first and second active areas; (c) forming a second dielectric layer over the first dielectric layer and the interconnection; (d) etching first and second contact holes adjacent to the opposite ends of the interconnection through the second and first dielectric layers, the first and second contact holes extending down to the first and second active area respectively; and (e) filling the first and second contact holes with first and second conductive plugs respectively, wherein the interconnection thereby connects the first and second conductive plugs to couple the first and second active areas.

摘要翻译： 本发明公开了一种新颖的镶嵌局部互连工艺，以避免由与隔离边缘的互连不良接口引起的结漏电。 该方法包括以下步骤：（a）在衬底表面上形成第一电介质层; （b）在电介质层的上层形成跨越第一和第二有源区的互连; （c）在第一介电层和互连之上形成第二电介质层; （d）通过第二和第一介电层蚀刻与互连的相对端相邻的第一和第二接触孔，第一和第二接触孔分别向下延伸到第一和第二有源区; 和（e）分别用第一和第二导电插塞填充第一和第二接触孔，其中互连由此连接第一和第二导电插塞以耦合第一和第二有源区域。

公开(公告)号：US06281059B1

公开(公告)日：2001-08-28

申请号：US09568495

申请日：2000-05-11

申请人： Hsin-Li Cheng ,  Chang-Da Yang

发明人： Hsin-Li Cheng ,  Chang-Da Yang

IPC分类号： H01L21336

CPC分类号： H01L27/0266

摘要： A method of forming ESD protective transistor is disclosed, which is performed by ion implant into the drain contact hole of the ESD protective transistor, wherein the contact hole are fabricated simultaneously with the gate contact holes of the functional transistor and of the ESD protective transistor. Both of the transistors have a respective metal silicide layer cap the polysilicon layer to prevent depleted region formed in the poly-gate for ion implant using p type ions. The p type ions are to increase the instant current tolerance. Alternatively, the ion implant is using n type ions to increase the punchthrough ability of the ESD protective transistor. In the latter case, the metal silicide layer in the gate regions of both transistors is optional.

摘要翻译： 公开了一种形成ESD保护晶体管的方法，其通过离子注入进入ESD保护晶体管的漏极接触孔中，其中接触孔与功能晶体管和ESD保护晶体管的栅极接触孔同时制造。 两个晶体管都具有相应的金属硅化物层覆盖多晶硅层，以防止在多晶硅中形成的用于使用p型离子的离子注入的耗尽区。 p型离子是提高瞬时电流公差。 或者，离子注入使用n型离子来增加ESD保护晶体管的穿通能力。 在后一种情况下，两个晶体管的栅极区域中的金属硅化物层是可选的。

公开(公告)号：US09269758B2

公开(公告)日：2016-02-23

申请号：US13005681

申请日：2011-01-13

申请人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

发明人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

IPC分类号： H01L29/40 ,  H01L49/02 ,  H01L27/06 ,  H01L27/08

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.

摘要翻译： 本公开涉及一种方法。 该方法包括提供包括顶表面的基底。 该方法还包括在衬底的顶表面上形成栅极。 形成的栅极具有从基板的顶表面测量的第一高度。 该方法还包括蚀刻栅极以将栅极减小到第二高度。 该第二高度明显小于第一高度。 本公开还涉及半导体器件。 半导体器件包括衬底。 衬底包括顶表面。 半导体器件还包括形成在衬底顶表面上的第一栅极。 第一个门有一个第一高度。 半导体器件还包括形成在衬底顶表面上的第二栅极。 第二个门有第二个高度。 第一高度大致小于第二高度。

公开(公告)号：US20090261450A1

公开(公告)日：2009-10-22

申请号：US12106759

申请日：2008-04-21

申请人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

发明人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.

摘要翻译： 介绍了电熔丝及其编程过程。 电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。 钨触点和硅化物层的颈部是电熔丝的可编程部分。 通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

公开(公告)号：US06559018B1

公开(公告)日：2003-05-06

申请号：US10053308

申请日：2002-01-18

申请人： Chi-Kang Liu ,  Tien-Chi Ke ,  Hsin-Li Cheng

发明人： Chi-Kang Liu ,  Tien-Chi Ke ,  Hsin-Li Cheng

IPC分类号： H01L21425

CPC分类号： H01L21/28518 ,  H01L21/28052 ,  H01L29/665

摘要： A new processing sequence is provided for the process of creating salicided layers of CoSix. A conventional gate electrode is formed up to the point where the process of salicidation has to be performed. At that time a layer of cobalt is deposited over the surface of the gate electrode, a first anneal is applied to the deposited layer of cobalt. The layer of cobalt is then selectively etched to formed the contact surfaces of the gate electrode after which, significantly and as a major deviation from previous methods of creating a salicided layer of CoSix, silicon is implanted into the surface of the created layer of CoSix. This silicon implant relieves a silicon deficiency into the first annealed layer of CoSix, this silicon deficiency has experimentally been determined as being the essential cause for the occurrence of Co—Si agglomeration after a second thermal anneal. After the silicon implantation has been completed, a second thermal anneal is applied to the created layer of CoSix. The occurrence of Co—Si agglomeration is in this manner essentially eliminated.

摘要翻译： 提供了一个新的处理顺序，用于创建CoSix的水浸层的过程。 形成常规的栅电极，直至必须进行盐化过程。 此时，在栅电极的表面上沉积钴层，首先对钴沉积层进行退火。 然后选择性地蚀刻钴层以形成栅电极的接触表面，之后，与先前创建CoSix的水杨酸层的方法相比，显着地和作为主要偏离，硅被植入到所产生的CoSix层的表面中。 这种硅植入物将硅缺陷释放到CoSix的第一退火层中，这种硅缺陷已经被确定为在第二热退火之后发生Co-Si聚集的重要原因。 在硅注入完成之后，将第二次热退火应用于所创建的CoSix层。 以这种方式基本上消除了Co-Si团聚的发生。

公开(公告)号：US20100090751A1

公开(公告)日：2010-04-15

申请号：US12637510

申请日：2009-12-14

申请人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

发明人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

IPC分类号： H01H85/00 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.

摘要翻译： 介绍了电熔丝及其编程过程。 电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。 钨触点和硅化物层的颈部是电熔丝的可编程部分。 通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

公开(公告)号：US07642176B2

公开(公告)日：2010-01-05

申请号：US12106759

申请日：2008-04-21

申请人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

发明人： Hsin-Li Cheng ,  Chia-Jung Lee ,  Chin-Shan Hou ,  Wei-Ming Chen

IPC分类号： H01L21/326 ,  H01L21/479

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An electrical fuse and a process of programming the same are presented. An electrical fuse comprises a lower level silicide layer on a non-doped or lightly-doped polysilicon layer, an upper level conductive layer, and a tungsten contact coupled between the lower level silicide layer and the upper level conductive layer. The tungsten contact and a neck portion of the silicide layer are the programmable portion of the electrical fuse. High post-programming resistance is achieved by a first programming phase that depletes silicide in the silicide layer, followed by a second programming phase that depletes tungsten in the tungsten contact.

摘要翻译： 介绍了电熔丝及其编程过程。 电熔丝包括在非掺杂或轻掺杂多晶硅层上的下层硅化物层，上层导电层和耦合在下层硅化物层和上层导电层之间的钨接触。 钨触点和硅化物层的颈部是电熔丝的可编程部分。 通过第一编程阶段实现高后编程电阻，其消耗硅化物层中的硅化物，随后是第二编程阶段，其消耗钨接触中的钨。

公开(公告)号：US20120181612A1

公开(公告)日：2012-07-19

申请号：US13005681

申请日：2011-01-13

申请人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

发明人： Jing-Hwang Yang ,  Chun-Heng Liao ,  Hsin-Li Cheng ,  Liang-Kai Han

IPC分类号： H01L29/40 ,  H01L21/3205

CPC分类号： H01L28/20 ,  H01L27/0629 ,  H01L27/0802

摘要： The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.

摘要翻译： 本公开涉及一种方法。 该方法包括提供包括顶表面的基底。 该方法还包括在衬底的顶表面上形成栅极。 形成的栅极具有从基板的顶表面测量的第一高度。 该方法还包括蚀刻栅极以将栅极减小到第二高度。 该第二高度明显小于第一高度。 本公开还涉及半导体器件。 半导体器件包括衬底。 衬底包括顶表面。 半导体器件还包括形成在衬底顶表面上的第一栅极。 第一个门有一个第一高度。 半导体器件还包括形成在衬底顶表面上的第二栅极。 第二个门有第二个高度。 第一高度大致小于第二高度。