公开(公告)号：US20250151479A1

公开(公告)日：2025-05-08

申请号：US18834168

申请日：2023-02-27

Applicant: MICLEDI MICRODISPLAYS BV ,  IMEC VZW ,  UNIVERSITEIT GENT

Inventor： Geert VAN STEENBERGE ,  Soeren STEUDEL

IPC: H10H20/851 ,  B82Y20/00 ,  H01L25/075 ,  H10H20/01 ,  H10H20/814 ,  H10H29/30

Abstract: An optoelectronic device (100) comprises a semiconductor light-emitting component (101) capable of emitting light at a first wavelength, a cavity (107) filled with a semiconductor wavelength conversion material (103) disposed in a path of the light emitted by the semiconductor light-emitting component (101) for converting the first wave-length into a second wavelength and a first multilayer interference reflector (105) provided at a bottom of the cavity (107) directed to the light-emitting component (101). The first multilayer interference reflector (105) is configured to be transmitive for the first wavelength and reflective for the second wavelength and a second multilayer interference reflector (106) is provided at a top (106′) and sidewalls (106″) of the cavity (107). The second multilayer interference reflector (106) is configured to be transmitive for the second wavelength and to be reflective for the first wavelength. An associated method of making the optoelectronic device is also provided.

公开(公告)号：US12279911B2

公开(公告)日：2025-04-22

申请号：US18042243

申请日：2021-07-01

Applicant: IMEC VZW

Inventor： Florian De Roose ,  Kris Myny

IPC: A61B8/00

Abstract: This patent disclosure relates to an ultrasound transducer including an array of ultrasound transducing elements, a plurality of transducer drive lines. The ultrasound transducer further includes an array of control circuits, wherein each individual control circuit includes a drive switch and a memory element, the drive switch comprising at least one thin-film transistor, the memory element being configured to store and control the state of the drive switch. The ultrasound transducer further configured so each individual ultrasound transducing element of the array of ultrasound transducing elements has one associated control circuit of the array of control circuits and one associated transducer drive line of the plurality of transducer drive lines, and wherein the ultrasound transducer is configured to, for each individual ultrasound transducing element, drive the individual ultrasound transducing element by the associated transducer drive line when the drive switch of the associated control circuit is in the on-state.

公开(公告)号：US20250118691A1

公开(公告)日：2025-04-10

申请号：US18906875

申请日：2024-10-04

Applicant: IMEC VZW

Inventor： Jaber Derakhshandeh ,  Eric Beyne

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor including a plurality of structured contacts suitable for forming electrical connections to respective contacts of another semiconductor component, wherein each of said structured contacts comprises a planar contact surface and a plurality of upright tube-shaped structures extending outward from the planar contact surface is disclosed. The tube-shaped structures may be arranged in a regular array on the respective contact surfaces and are produced by a sequence of steps including the patterning of a dielectric layer formed on the front surface of the component, said patterning resulting in openings in said dielectric layer, and the deposition of a conformal layer on said patterned dielectric layer, thereby lining the bottom and sidewalls of the openings. The conformal layer may be removed from the upper surface of the dielectric layer and the material of said layer is removed selectively with respect to the conformal layer, resulting in said tube-shaped structures.

公开(公告)号：US20250098336A1

公开(公告)日：2025-03-20

申请号：US18882961

申请日：2024-09-12

Applicant: IMEC VZW ,  UNIVERSITEIT HASSELT

Inventor： Tom BORGERS ,  Jonathan GOVAERTS

IPC: H01L31/0443 ,  H01L31/05

Abstract: A photovoltaic module includes at least one string of solar cells wherein the solar cells are electrically connected in series using a plurality of connecting elements, wherein each connecting element electrically connects a frontside of one of the solar cells of the at least one string with a backside of the neighboring solar cell of the at least one string; a weave of electrically insulating yarns on which the solar cells are positioned; at least one electronic device comprising a first terminal, and a second terminal, wherein the at least one electronic device is fixed to the weave and wherein the first terminal, and the second terminal are respectively electrically connected with the connecting elements at the backsides of neighboring solar cells of the at least one string.

公开(公告)号：US12249970B2

公开(公告)日：2025-03-11

申请号：US17280105

申请日：2019-09-24

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy Torfs ,  Michiel Verplaetse

IPC: H03H17/02 ,  H03H15/02 ,  H03H17/06

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

公开(公告)号：US12237371B2

公开(公告)日：2025-02-25

申请号：US17476747

申请日：2021-09-16

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

IPC: H01L29/06 ,  H01L29/786

Abstract: A method for forming a semiconductor device is provided. The method comprises forming a device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over the topmost channel layer, wherein the top sacrificial layer is thicker than each lower sacrificial layer; etching the top sacrificial layer to form a top sacrificial layer portion underneath the sacrificial gate structure; forming a first spacer on end surfaces of the top sacrificial layer portion; etching the channel and lower sacrificial layers while using the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions; etching the lower sacrificial layer portions to form recesses in the device layer stack, while the first spacer masks the end surfaces of the top sacrificial layer portion; and forming a second spacer in the recesses.

公开(公告)号：US20250048690A1

公开(公告)日：2025-02-06

申请号：US18715354

申请日：2021-12-02

Applicant: IMEC VZW ,  Huawei Technologies Co., Ltd.

Inventor： Bilal CHEHAB ,  Krishna Kumar BHUWALKA ,  Julien RYCKAERT

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).

公开(公告)号：US12216057B2

公开(公告)日：2025-02-04

申请号：US17371609

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Thomas Nuytten ,  Janusz Bogdanowicz

IPC: G01N21/65 ,  H01L21/66

Abstract: A method and apparatus are provided for a spectroscopic measurement for determining a lateral recess depth in the sidewall of a microstructure. The structure is formed on a larger substrate with the sidewall in an upright position relative to the substrate, and the recess extends essentially parallel to the substrate. The recess may be an etch depth obtained by etching a first layer relative to two adjacent layers, the layers oriented parallel to the substrate, the etch process progressing inward from the sidewall. An incident energy beam falling on the structure generates a spectroscopic response captured and processed respectively by a detector and a processing unit. The response comprises one or more peaks related to the material or materials of the substrate and the structure. According to the method, a parameter is derived from said one or more peaks, that is representative of the lateral recess depth.

公开(公告)号：US20250012895A1

公开(公告)日：2025-01-09

申请号：US18763273

申请日：2024-07-03

Applicant: IMEC VZW

Inventor： Hamed Javadi ,  Hichem Sahli ,  Andre Bourdoux

IPC: G01S7/41 ,  G01S13/90

Abstract: A system includes at least two photovoltaic modules each comprising a respective module area being substantially perpendicular to the thickness of the corresponding photovoltaic module. Each of the at least two module areas comprises at least one of two first sides being substantially perpendicular to the thickness of the corresponding photovoltaic module and/or two second sides being substantially perpendicular to the thickness of the corresponding photovoltaic module. In this context, the at least two module areas are arranged in a substantially parallel manner with respect to each other and are shifted with respect to each other in an extension direction of the system. In addition to this, the at least two module areas are arranged in a staggering or alternating or ascending or descending manner with respect to an extension plane in the extension direction of t

公开(公告)号：US12191880B2

公开(公告)日：2025-01-07

申请号：US18083823

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Ewout Martens ,  Jan Craninckx

IPC: H03M1/16 ,  H03M1/12 ,  H03M1/56

Abstract: A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.