公开(公告)号：US12249970B2

公开(公告)日：2025-03-11

申请号：US17280105

申请日：2019-09-24

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy Torfs ,  Michiel Verplaetse

IPC: H03H17/02 ,  H03H15/02 ,  H03H17/06

Abstract: A filter includes cascaded building blocks, for filtering an incoming signal. Each building block has first and second delay elements. A first scaling device is between an input node of the first delay element and an output node of the second delay element, and a second scaling device is between an output node of the first delay element and an input node of the second delay element. The building block has a cross scaling device between the output nodes of the first delay element and of the second delay element, and/or between the input nodes of the first delay element and of the second delay element. The building block is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.

公开(公告)号：US11368164B2

公开(公告)日：2022-06-21

申请号：US17284661

申请日：2019-10-11

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy Torfs ,  Hannes Ramon ,  Xin Yin

IPC: H03K9/00 ,  H03M1/66 ,  H03M1/08

Abstract: An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.

公开(公告)号：US10567083B2

公开(公告)日：2020-02-18

申请号：US15907534

申请日：2018-02-28

Applicant: Universiteit Gent ,  IMEC vzw

Inventor： Guy Torfs ,  Johan Bauwelinck ,  Haolin Li ,  Laurens Breyne

IPC: H04B10/2575 ,  H04B10/50 ,  H04B10/516

Abstract: A communication system is provided for transmitting a RF signal, which has a frequency band. The communication system comprises: a sigma delta modulator for modulating the RF signal into a broadband signal wherein the signal to noise ratio of the broadband signal is higher in the frequency band of the RF signal than outside the frequency band of the RF signal; an optical transmitter connected with the sigma delta modulator and with an optical fiber for transmitting the broadband signal over the optical fiber; a photo-detector configured for receiving the broadband signal from the optical fiber and converting it into an electrical signal; an output device and a matching circuit configured for power matching and/or noise matching of the photo-detector, at the frequency band of the RF signal, with the output device.

公开(公告)号：US09369317B2

公开(公告)日：2016-06-14

申请号：US14634176

申请日：2015-02-27

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Jeffrey Sinsky ,  Geert de Peuter ,  Guy Torfs ,  Zhisheng Li ,  Timothy De Keulenaer

IPC: H03M1/12 ,  H03M1/36 ,  H04B10/60 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H03M1/1215 ,  H03M1/361 ,  H04B10/60

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract translation: 用于将多电平信号转换成具有周期T并且包括n个信号电平的至少一个二进制信号的电路包括比较和分离电路，其配置用于将多电平信号的值与（n-1）个不同参考值 并且具有N组（n-1）个输出端子，用于输出指示多电平信号的值是否低于或高于（n-1）个参考值的N组（n-1）个输出信号。 电路还包括具有输入和输出的N组（n-1）采样保持电路，并被配置为在时钟周期N * T下工作，其中每个输出端连接到采样保持电路的输入端， 保持电路。 此外，电路包括连接到N组（n-1）个采样和保持电路的输出的逻辑电路，用于产生具有周期N * T的至少一个二进制信号。

公开(公告)号：US09124251B2

公开(公告)日：2015-09-01

申请号：US14192551

申请日：2014-02-27

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Christophe Van Praet ,  Guy Torfs ,  Johan Bauwelinck ,  Jan Vandewege

IPC: H03H11/12 ,  H03K3/012 ,  H03H11/04 ,  H03F3/45 ,  H03F3/50

CPC classification number: H03K3/012 ,  H03F3/45179 ,  H03F3/505 ,  H03H11/0405 ,  H03H11/12 ,  H03H11/1213

Abstract: A filter, comprising: two source-follower stages connected in series and in between input nodes and output nodes, wherein inner nodes connect the two stages; and a frequency dependent feedback circuit connected between the input and output nodes, wherein the filter comprises additional frequency dependent feedback circuits connected between input nodes and inner nodes and between output nodes and inner nodes, the additional frequency dependent feedback circuits comprising capacitors.

Abstract translation: 一种滤波器，包括：串联连接在输入节点和输出节点之间的两个源跟随器级，其中内部节点连接两个级; 以及连接在所述输入和输出节点之间的频率相关反馈电路，其中所述滤波器包括连接在输入节点和内部节点之间以及在输出节点和内部节点之间的额外的频率相关反馈电路，所述附加的频率相关反馈电路包括电容器

公开(公告)号：US20150244547A1

公开(公告)日：2015-08-27

申请号：US14634176

申请日：2015-02-27

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Jeffrey Sinsky ,  Geert de Peuter ,  Guy Torfs ,  Zhisheng Li ,  Timothy De Keulenaer

IPC: H04L25/49 ,  H04B10/60

CPC classification number: H04L25/4917 ,  H03M1/1215 ,  H03M1/361 ,  H04B10/60

Abstract: Circuitry for converting a multi-level signal into at least one binary signal, having a period T and comprising n signal levels, includes comparing and splitting circuitry configured for comparing a value of the multi-level signal with (n−1) different reference values, and having N sets of (n−1) output terminals for outputting N sets of (n−1) output signals indicating whether the value of the multi-level signal is below or above the (n−1) reference values. The circuitry also includes N sets of (n−1) sample-and-hold circuits having an input and an output and being configured for operating at a clock period N*T, wherein each output terminal is connected to the input of a sample-and-hold circuit. Further, the circuitry includes logical circuitry connected to the outputs of the N sets of (n−1) sample-and-hold circuits for generating at least one binary signal having a period N*T.

Abstract translation: 用于将多电平信号转换成具有周期T并且包括n个信号电平的至少一个二进制信号的电路包括比较和分离电路，其配置用于将多电平信号的值与（n-1）个不同参考值 并且具有N组（n-1）个输出端子，用于输出指示多电平信号的值是否低于或高于（n-1）个参考值的N组（n-1）个输出信号。 电路还包括具有输入和输出的N组（n-1）采样保持电路，并被配置为在时钟周期N * T下工作，其中每个输出端连接到采样保持电路的输入端， 保持电路。 此外，电路包括连接到N组（n-1）个采样和保持电路的输出的逻辑电路，用于产生具有周期N * T的至少一个二进制信号。

公开(公告)号：US11342995B2

公开(公告)日：2022-05-24

申请号：US17283706

申请日：2019-10-08

Applicant: UNIVERSITEIT GENT ,  IMEC VZW

Inventor： Guy Torfs ,  Piet Wambacq

IPC: H04B10/2575 ,  H04B10/25 ,  H04B10/2507

Abstract: A communication system includes a base station, at least one remote radio head, and at least one channel. The base station has at least two digital modulators adapted for modulating a first and a second incoming radio signal to obtain a first and a second quantized signal, a multiplexer for interleaving the quantized signals, and a transmitter adapted for transmitting the resulting quantized signal over the channel to the remote radio head. The remote radio head includes a receiver adapted for capturing the quantized signal, a clock extraction module adapted for converting the signal from the receiver into a clock signal, a demultiplexer for splitting the quantized signal using the clock signal to obtain at least two quantized signals, and a filter adapted for removing quantization noise from the quantized signal from the receiver or the demultiplexer.

公开(公告)号：US20150276873A1

公开(公告)日：2015-10-01

申请号：US14668415

申请日：2015-03-25

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Johan Bauwelinck ,  Guy Torfs ,  Yu Ban ,  Timothy De Keulenaer

IPC: G01R31/3177 ,  H04L25/03

CPC classification number: H04L25/03891 ,  G01R31/3181 ,  H04L25/03019 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03878 ,  H04L2025/0349 ,  H04N7/52 ,  H04N19/137 ,  H04N19/14 ,  H04N19/176 ,  H04N19/61

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract translation: 这里描述的是前馈均衡器，其配置为在正常操作模式和测试操作模式下操作。 前馈均衡器具有用于正常操作模式的输入端口和输出端口。 前馈均衡器中提供了测试输入端口和测试输出端口，用于测试操作模式。 可以提供缓冲器以匹配输入，输出，测试输入和测试输出端口中的各个的阻抗。 前馈均衡器允许在开发期间进行测试，并且一旦安装在集成电路中，而不会干扰正常的操作模式。

公开(公告)号：US09432225B2

公开(公告)日：2016-08-30

申请号：US14668415

申请日：2015-03-25

Applicant: IMEC VZW ,  Universiteit Gent

Inventor： Johan Bauwelinck ,  Guy Torfs ,  Yu Ban ,  Timothy De Keulenaer

IPC: H04L25/03 ,  G01R31/3181 ,  H04N19/176 ,  H04N19/61 ,  H04N19/136 ,  H04N19/137

CPC classification number: H04L25/03891 ,  G01R31/3181 ,  H04L25/03019 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03133 ,  H04L25/03878 ,  H04L2025/0349 ,  H04N7/52 ,  H04N19/137 ,  H04N19/14 ,  H04N19/176 ,  H04N19/61

Abstract: Described herein is a feed forward equalizer that is configured to operate in a normal operational mode and in a test operational mode. The feed forward equalizer has an input port and an output port which are used for the normal operational mode. A test input port and a test output port are provided in the feed forward equalizer, and are used for the test operational mode. Buffers may be provided for matching the impedance of respective ones of the input, output, test input, and test output ports. The feed forward equalizer allows testing during development, and once mounted in an integrated circuit, without interfering with the normal operational mode.

Abstract translation: 这里描述的是前馈均衡器，其配置为在正常操作模式和测试操作模式下操作。 前馈均衡器具有用于正常操作模式的输入端口和输出端口。 前馈均衡器中提供了测试输入端口和测试输出端口，用于测试操作模式。 可以提供缓冲器以匹配输入，输出，测试输入和测试输出端口中的各个的阻抗。 前馈均衡器允许在开发期间进行测试，并且一旦安装在集成电路中，而不会干扰正常的操作模式。

公开(公告)号：US20150280950A1

公开(公告)日：2015-10-01

申请号：US14669965

申请日：2015-03-26

Applicant: IMEC VZW ,  UNIVERSITEIT GENT

Inventor： Timothy De Keulenaer ,  Renato Vaernewyck ,  Johan Bauwelinck ,  Guy Torfs

IPC: H04L27/06

CPC classification number: H04L27/06 ,  H03M5/12 ,  H03M5/16

Abstract: Described herein is a multi-level to binary converter in which a cascade of differential limiting amplifiers are utilised for each signal path to provide both increased gain and increased bandwidth without having to trade one off against the other. Where the multi-level data is duobinary, cascaded amplifiers are coupled to a XOR logic gate. In each path, a copy of the duobinary signal is level shifted using an adjustable threshold before amplification in an amplifier. The shifted and amplified signal is then fed to another amplifier where it undergoes the same steps. The outputs from each path are fed to the XOR logic gate to generate the desired binary signal, corresponding to a decoded synchronized NRZ data stream. Such a multi-level to binary converter is capable of performing at data rates of 50 to 80 Gb/s and above, and can easily be integrated within a chip for high-speed electrical backplane communication, optical backplanes or optical fibre links.

Abstract translation: 这里描述的是一种多电平到二进制转换器，其中使用级联的差分限幅放大器用于每个信号路径以提供增加的增益和增加的带宽，而不必相互抵销另一个。 多级数据是双向的，级联放大器耦合到异或逻辑门。 在每个路径中，在放大器放大之前，使用可调阈值对二进制信号的副本进行电平移位。 然后将移位和放大的信号馈送到另一个放大器，在那里它经历相同的步骤。 来自每个路径的输出被馈送到异或逻辑门以产生对应于解码的同步NRZ数据流的所需二进制信号。 这样的多电平到二进制转换器能够以50至80Gb / s及以上的数据速率执行，并且可以容易地集成在用于高速电底板通信，光学背板或光纤链路的芯片内。