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公开(公告)号：US20250036752A1
公开(公告)日：2025-01-30
申请号：US18713110
申请日：2022-10-20
Inventor： Zhe Wang , Chenggang Wu , Mengyao Xie
Abstract: A CET mechanism-based method for protecting the integrity of a general-purpose memory. In the method, the integrity of the general-purpose memory is protected on the basis of a CET mechanism. A dedicated shadow stack page is provided, and is independent of the shadow stack page maintained by the CET mechanism itself, and overhead reduction processing adaptive to content to be written that is written to the dedicated shadow stack page and requires writing overhead reduction is performed on the content to be written, so as to reduce the number of times of using WRSS instructions, such that the integrity of sensitive data and/or sensitive codes is protected in the case of using lower overhead, and performance overhead of a processor in the protection of the integrity of the general-purpose memory is reduced, thereby improving the efficiency of processing other tasks by the processor.
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公开(公告)号：US11841733B2
公开(公告)日：2023-12-12
申请号：US17791511
申请日：2020-01-08
Inventor： Ke Zhang , Yazhou Wang , Mingyu Chen , Yisong Chang , Ran Zhao , Yungang Bao
IPC: G06F13/42
CPC classification number: G06F13/4282
Abstract: A method and system for realizing a FPGA server, wherein centralized monitoring and managing all SoC FPGA compute nodes within the server by a motherboard, the motherboard comprising: a plurality of self-defined management interfaces for connecting the SoC FPGA compute nodes to supply power and data switch to the SoC FPGA compute nodes; a management network switch module for interconnecting the SoC FPGA compute nodes and supplying management; and a core control unit for managing the SoC FPGA compute nodes through the self-defined management interfaces and a self-defined management interface protocol, and acquiring operating parameters of the SoC FPGA compute nodes to manage and monitor the SoC FPGA compute nodes based on the management interface protocol.
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公开(公告)号：US20230101208A1
公开(公告)日：2023-03-30
申请号：US17791511
申请日：2020-01-08
Inventor： Ke ZHANG , Yazhou WANG , Mingyu CHEN , Yisong CHANG , Ran ZHAO , Yungang BAO
IPC: G06F13/42
Abstract: A method and system for realizing a FPGA server, wherein centralized monitoring and managing all SoC FPGA compute nodes within the server by a motherboard, the motherboard comprising: a plurality of self-defined management interfaces for connecting the SoC FPGA compute nodes to supply power and data switch to the SoC FPGA compute nodes; a management network switch module for interconnecting the SoC FPGA compute nodes and supplying management; and a core control unit for managing the SoC FPGA compute nodes through the self-defined management interfaces and a self-defined management interface protocol, and acquiring operating parameters of the SoC FPGA compute nodes to manage and monitor the SoC FPGA compute nodes based on the management interface protocol.
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4.发明授权公开(公告)号：US11616662B2
公开(公告)日：2023-03-28
申请号：US17100570
申请日：2020-11-20
Inventor： Jinhua Tao , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/44 , H04L45/16 , H04L49/109
Abstract: The present invention provides a fractal tree structure-based data transmit device and method, a control device, and an intelligent chip. The device comprises: a central node that is as a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; the plurality of leaf nodes that are as communication data nodes of the network-on-chip and for transmitting the communication data to a central leaf node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data; the central node, the forwarder modules and the plurality of leaf nodes are connected in the fractal tree network structure, and the central node is directly connected to M the forwarder modules and/or leaf nodes, any the forwarder module is directly connected to M the next level forwarder modules and/or leaf nodes.
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公开(公告)号：US20220374733A1
公开(公告)日：2022-11-24
申请号：US17761220
申请日：2019-12-27
Inventor： Gaogang XIE , Xinyi ZHANG , Penghao ZHANG
Abstract: The disclosure provides a data packet classification method and system based on a convolutional neural network including merging each rule set in a training rule set to form a plurality of merging schemes, and determining an optimal merging scheme for each rule set in the training rule set on the basis of performance evaluation; converting a prefix combination distribution of each rule set in the training rule set and a target rule set into an image, and training a convolutional neural network model by taking the image and the corresponding optimal merging scheme as features; and classifying the target rule set on the basis of image similarity, and constructing a corresponding hash table for data packet classification.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11488000B2
公开(公告)日：2022-11-01
申请号：US15770457
申请日：2016-06-17
Inventor： Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure provides an operation apparatus and method for an acceleration chip for accelerating a deep neural network algorithm. The apparatus comprises: a vector addition processor module and a vector function value arithmetic unit and a vector multiplier-adder module wherein the three modules execute a programmable instruction, and interact with each other to calculate values of neurons and a network output result of a neural network, and a variation amount of a synaptic weight representing the interaction strength of the neurons on an input layer to the neurons on an output layer; and the three modules are all provided with an intermediate value storage region and perform read and write operations on a primary memory.
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公开(公告)号：US20210350214A1
公开(公告)日：2021-11-11
申请号：US17250892
申请日：2019-05-21
Inventor： Xiaowei LI , Xin WEI , Hang LU
Abstract: Disclosed embodiments relate to a convolutional neural network computing method and system based on weight kneading, comprising: arranging original weights in a computation sequence and aligning by bit to obtain a weight matrix, removing slack bits in the weight matrix, allowing essential bits in each column of the weight matrix to fill the vacancies according to the computation sequence to obtain an intermediate matrix, removing null rows in the intermediate matrix, obtain a kneading matrix, wherein each row of the kneading matrix serves as a kneading weight; obtaining positional information of the activation corresponding to each bit of the kneading weight; divides the kneading weight by bit into multiple weight segments, processing summation of the weight segments and the corresponding activations according to the positional information, and sending a processing result to an adder tree to obtain an output feature map by means of executing shift-and-add on the processing result.
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公开(公告)号：US20190087716A1
公开(公告)日：2019-03-21
申请号：US16079525
申请日：2016-08-09
Inventor： Zidong DU , Qi GUO , Tianshi CHEN , Yunji CHEN
Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.
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公开(公告)号：US20180329681A1
公开(公告)日：2018-11-15
申请号：US15773959
申请日：2016-06-17
Inventor： Shijin Zhang , Tao Luo , Shaoli Liu , Yunji Chen
Abstract: The present disclosure provides a quick operation device for a nonlinear function, and a method therefor. The device comprises: a domain conversion part for converting an input independent variable into a corresponding value in a table lookup range; a table lookup part for looking up a slope and an intercept of the corresponding piecewise linear fitting based on the input independent variable or an independent variable processed by the domain conversion part; and a linear fitting part for obtaining, a final result in a way of linear fitting based on the slope and the intercept obtained, by means of table lookup, by the table lookup part. The present disclosure solves the problems of slow operation speed, large area of the operation device, and high power consumption caused by the traditional method.
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公开(公告)号：US20180321944A1
公开(公告)日：2018-11-08
申请号：US15773970
申请日：2016-06-17
Inventor： Daofu LIU , Shengyuan ZHOU , Yunji CHEN
IPC: G06F9/30
CPC classification number: G06F9/30105 , G06F9/30021 , G06F9/3012 , G06F17/30
Abstract: The present disclosure relates to a data ranking apparatus that comprises: a register group for storing K pieces of temporarily ranked maximum or minimum data in a data ranking process, the register group comprises a plurality of registers connected in parallel, and two adjacent registers unidirectionally transmit data from a low level to a high level; a comparator group, which comprises a plurality of comparators connected to the registers on a one-to-one basis, compares the size relationship among a plurality of pieces of input data, and outputs the data of larger or smaller value to the corresponding registers; and a control circuit generating a plurality of flag bits applying to the registers, wherein the flag bits are used to judge whether the registers receive data transmitted from corresponding comparators or lower-level registers, and judge whether the registers transmit data to high level registers.
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