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74 条记录 (耗时 0.017 秒)

    NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES
    2.
    发明申请
    NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES 有权
    非易失性存储器电路，包括具有相变存储器件的电压分压器

    公开(公告)号：US20100177560A1

    公开(公告)日：2010-07-15

    申请号：US12354121

    申请日：2009-01-15

    申请人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    发明人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    IPC分类号： G11C11/00

    CPC分类号： G11C14/009 ,  G11C13/0004

    摘要： A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.

    摘要翻译： 描述了包括具有第一相变存储器（PCM）装置的分压器和耦合到第一PCM装置的第二PCM装置的存储器电路。 在一个实施例中，第一PCM器件处于设定电阻状态，第二PCM器件处于复位电阻状态。 而且，在一个实施例中，分压器还包括耦合到第一PCM器件的第一开关和耦合到第一开关和第二PCM器件的第二开关。 在一个实施例中，存储器电路还包括耦合到分压器的半锁存器和耦合到半锁存器和分压器的级联晶体管。

    Sense amplifier with individually optimized high and low power modes
    7.
    发明授权
    Sense amplifier with individually optimized high and low power modes 失效
    感应放大器，具有单独优化的高功率和低功耗模式

    公开(公告)号：US5850365A

    公开(公告)日：1998-12-15

    申请号：US772567

    申请日：1996-12-24

    申请人： Dirk A. Reese ,  Myron W. Wong ,  John C. Costello

    发明人： Dirk A. Reese ,  Myron W. Wong ,  John C. Costello

    IPC分类号： G11C7/06 ,  G11C7/02

    CPC分类号： G11C7/067

    摘要： The present invention is a sense amplifier circuit for use with programmable logic devices that provides improved switching time by actively limiting the voltage swing on the bit line which it is sensing, rather than passively sensing the voltage, employs feedback circuits to further improve switching time and may be selectively operated in low power mode without significant reduction in switching speed. Voltage reference control circuitry, comprising variable current limiters controlled by the potential of a supply of reference potential, can be added to improve noise immunity. The circuitry of the supply of reference potential is designed so that its sensitivity to fabrication variations is substantially similar to that of the sense amplifier and so that it adjusts the reference potential accordingly.

    摘要翻译： 本发明是一种与可编程逻辑器件一起使用的读出放大器电路，通过主动地限制其正在感测的位线上的电压摆幅而不是被动地感测电压来提供改进的开关时间，采用反馈电路来进一步提高开关时间， 可以选择性地在低功率模式下操作而不显着降低开关速度。 可以添加包括由参考电位供应的电位控制的可变电流限制器的电压参​​考控制电路，以提高抗噪声性能。 设计参考电位的电路被设计成使得其对制造变化的敏感度基本上类似于读出放大器的灵敏度，并因此相应地调整参考电位。

    Programmable logic device macrocell with improved logic capability
    10.
    发明授权
    Programmable logic device macrocell with improved logic capability 失效
    具有改进逻辑能力的可编程逻辑器件宏单元

    公开(公告)号：US06366119B1

    公开(公告)日：2002-04-02

    申请号：US09677156

    申请日：2000-10-02

    申请人： Bruce B. Pedersen ,  John C. Costello

    发明人： Bruce B. Pedersen ,  John C. Costello

    IPC分类号： H03K19177

    CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17748

    摘要： A macrocell for a programmable logic device includes circuitry for allowing a neighboring macrocell to borrow various numbers of the product terms of the macrocell. The macrocell can continue to make full use of its product terms that are not thus borrowed. This includes logically combining and registering the unborrowed product terms. The macrocell may include circuitry for feeding back to the AND array of the programmable logic device a combinatorial or registered signal of the macrocell, and also outputting such a combinatorial or registered signal from the macrocell. When a combinatorial signal is fed back, the register of the macrocell can be used for another signal of the macrocell.

    摘要翻译： 用于可编程逻辑器件的宏单元包括用于允许相邻宏单元借用宏单元的各种数量的乘积项的电路。 宏单元可以继续充分利用其不被借用的产品术语。 这包括逻辑上组合和注册未管理的产品术语。 宏单元可以包括用于将可编程逻辑器件的AND阵列反馈给宏单元的组合或注册信号的电路，并且还从宏单元输出这样的组合或注册信号。 当反馈组合信号时，宏单元的寄存器可用于宏单元的另一个信号。