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    Non-volatile memory circuit including voltage divider with phase change memory devices
    1.
    发明授权
    Non-volatile memory circuit including voltage divider with phase change memory devices 有权
    包括具有相变存储器件的分压器的非易失性存储器电路

    公开(公告)号：US08130538B2

    公开(公告)日：2012-03-06

    申请号：US12354121

    申请日：2009-01-15

    申请人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    发明人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    IPC分类号： G11C11/00

    CPC分类号： G11C14/009 ,  G11C13/0004

    摘要： A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.

    摘要翻译： 描述了包括具有第一相变存储器（PCM）装置的分压器和耦合到第一PCM装置的第二PCM装置的存储器电路。 在一个实施例中，第一PCM器件处于设定电阻状态，第二PCM器件处于复位电阻状态。 而且，在一个实施例中，分压器还包括耦合到第一PCM器件的第一开关和耦合到第一开关和第二PCM器件的第二开关。 在一个实施例中，存储器电路还包括耦合到分压器的半锁存器和耦合到半锁存器和分压器的级联晶体管。

    NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES
    2.
    发明申请
    NON-VOLATILE MEMORY CIRCUIT INCLUDING VOLTAGE DIVIDER WITH PHASE CHANGE MEMORY DEVICES 有权
    非易失性存储器电路，包括具有相变存储器件的电压分压器

    公开(公告)号：US20100177560A1

    公开(公告)日：2010-07-15

    申请号：US12354121

    申请日：2009-01-15

    申请人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    发明人： Peter J. McElheny ,  Richard G. Smolen ,  John C. Costello

    IPC分类号： G11C11/00

    CPC分类号： G11C14/009 ,  G11C13/0004

    摘要： A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.

    摘要翻译： 描述了包括具有第一相变存储器（PCM）装置的分压器和耦合到第一PCM装置的第二PCM装置的存储器电路。 在一个实施例中，第一PCM器件处于设定电阻状态，第二PCM器件处于复位电阻状态。 而且，在一个实施例中，分压器还包括耦合到第一PCM器件的第一开关和耦合到第一开关和第二PCM器件的第二开关。 在一个实施例中，存储器电路还包括耦合到分压器的半锁存器和耦合到半锁存器和分压器的级联晶体管。

    Process for making an EEPROM active area castling
    3.
    发明授权
    Process for making an EEPROM active area castling 失效
    制造EEPROM活动区域铸造的过程

    公开(公告)号：US06187634B1

    公开(公告)日：2001-02-13

    申请号：US09045737

    申请日：1998-03-19

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11519 ,  H01L27/0203 ,  Y10S438/942

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    EEPROM active area castling
    4.
    发明授权
    EEPROM active area castling 失效
    EEPROM活动区域

    公开(公告)号：US06624467B1

    公开(公告)日：2003-09-23

    申请号：US10193085

    申请日：2002-07-09

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L29788

    CPC分类号： H01L27/11519 ,  H01L27/0203

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    Castled active area mask
    5.
    发明授权
    Castled active area mask 失效
    壁挂活动区域面罩

    公开(公告)号：US06472272B1

    公开(公告)日：2002-10-29

    申请号：US09733850

    申请日：2000-12-08

    申请人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    发明人： Peter J. McElheny ,  Raminda U. Madurawe ,  Richard G. Smolen ,  Minchang Liang

    IPC分类号： H01L21336

    CPC分类号： H01L27/11519 ,  H01L27/0203 ,  Y10S438/942

    摘要： Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

    摘要翻译： 提供了一个“castled”活动区域面罩。 壁挂式有源区掩模是延长超过其与隧道电介质的预期交点的形式的有源区掩模，以形成EEPROM单元的隧道窗口，并且还在扩展的至少一部分中加宽。 例如，在一个优选实施例中，城堡延伸部可以具有“T”形状。 由这种掩模产生的拱形有源区域在到达EEPROM单元的TD窗口之前提供缓冲器以吸收场氧化物侵入。 根据本发明的掩模可以用于制造由于场氧化物侵入而不受TD窗口尺寸变化的EEPROM单元以及增加密度的EEPROM单元阵列。

    Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers
    8.
    发明授权
    Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers 有权
    具有增强的栅耗尽层的金属氧化物半导体晶体管的集成电路

    公开(公告)号：US07812408B1

    公开(公告)日：2010-10-12

    申请号：US11975010

    申请日：2007-10-16

    申请人： Albert Ratnakumar ,  Peter J. McElheny

    发明人： Albert Ratnakumar ,  Peter J. McElheny

    IPC分类号： H01L27/088

    CPC分类号： H01L21/82345 ,  H01L21/823462 ,  H01L27/088

    摘要： An integrated circuit is provided with groups of transistors that handle different maximum voltage levels. The transistors may be metal-oxide-semiconductor transistors having body, source, drain, and gate terminals. The gate of each transistor may have a gate insulator and a gate conductor. The gate conductor may be formed from a semiconductor such as polysilicon. Adjacent to the gate insulator, the polysilicon gate conductor may have a depletion layer. The depletion layer may have a thickness that is related to the doping level in the polysilicon gate conductor. By reducing the doping level in the polysilicon gates of some of the transistors, the equivalent oxide thickness of those transistors is increased, thereby enhancing their ability to withstand elevated voltages without experiencing gate oxide breakdown due to hot carrier injection effects.

    摘要翻译： 集成电路设置有处理不同最大电压电平的晶体管组。 晶体管可以是具有主体，源极，漏极和栅极端子的金属氧化物半导体晶体管。 每个晶体管的栅极可以具有栅极绝缘体和栅极导体。 栅极导体可以由诸如多晶硅的半导体形成。 与栅极绝缘体相邻，多晶硅栅极导体可以具有耗尽层。 耗尽层可以具有与多晶硅栅极导体中的掺杂水平相关的厚度。 通过降低一些晶体管的多晶硅栅极中的掺杂水平，这些晶体管的等效氧化物厚度增加，从而增强了其承受高电压的能力，而不会由于热载流子注入效应而经历栅极氧化物击穿。

    Field emission erasable programmable read-only memory
    9.
    发明授权
    Field emission erasable programmable read-only memory 失效
    场发射可擦除可编程只读存储器

    公开(公告)号：US06038171A

    公开(公告)日：2000-03-14

    申请号：US953849

    申请日：1997-10-15

    申请人： Peter J. McElheny

    发明人： Peter J. McElheny

    IPC分类号： G11C16/04 ,  G11C16/14 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788

    CPC分类号： G11C16/0408 ,  G11C16/14 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

    摘要： Disclosed is a field-emission erasable programmable read-only memory cell which includes one or more field-emission tips on one or more layers of the cell. The cell is programmable and/or erasable by electron emission from the emission tips. Methods of making and using this field-emission erasable programmable read-only memory (FEEPROM) cell are also provided.

    摘要翻译： 公开了一种场发射可擦除可编程只读存储器单元，其包括在该单元的一个或多个层上的一个或多个场致发射尖端。 电池通过来自发射端的电子发射是可编程的和/或可擦除的。 还提供了制造和使用该场发射可擦除可编程只读存储器（FEEPROM）单元的方法。

    Integrated circuit and a method to optimize strain inducing composites
    10.
    发明授权
    Integrated circuit and a method to optimize strain inducing composites 有权
    集成电路和优化应变诱导复合材料的方法

    公开(公告)号：US08765541B1

    公开(公告)日：2014-07-01

    申请号：US13214056

    申请日：2011-08-19

    申请人： Girish Venkitachalam ,  Che Ta Hsu ,  Fangyun Richter ,  Peter J. McElheny

    发明人： Girish Venkitachalam ,  Che Ta Hsu ,  Fangyun Richter ,  Peter J. McElheny

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/267

    摘要： A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.

    摘要翻译： 公开了一种设计IC的方法，以提供应变诱导复合材料的均匀沉积。 设计IC的方法包括：确定IC设计上的总应变诱导沉积区域。 然后，将总应变诱导沉积区域与预定尺寸进行比较。 当总应变诱导沉积面积低于预定尺寸时，修改虚拟扩散区域以增加总应变诱导沉积面积。 最后，应变诱导沉积区域被优化。 还公开了制造IC和IC的方法。