公开(公告)号：US08543755B2

公开(公告)日：2013-09-24

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/36

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。

公开(公告)号：US08375234B2

公开(公告)日：2013-02-12

申请号：US12033433

申请日：2008-02-19

申请人： Michal Schramm ,  Ziv Hershman ,  Yehezkel Friedman ,  Zeev Heller

发明人： Michal Schramm ,  Ziv Hershman ,  Yehezkel Friedman ,  Zeev Heller

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power.

摘要翻译： 总线未通电时通用串行总线唤醒。 在一个实施例中，一种从非供电状态唤醒通用串行总线（USB）的方法包括：在检测到唤醒条件时，与USB设备相关联的唤醒生成模块在生成唤醒条件的电力线上产生唤醒信号 USB总线，耦合到USB设备，或在单线边带上; 以及主机唤醒模块，其检测所述唤醒信号并且使与所述USB设备耦合的所述USB总线被供电。

公开(公告)号：US20090210734A1

公开(公告)日：2009-08-20

申请号：US12033433

申请日：2008-02-19

申请人： Michal Schramm ,  Ziv Hershman ,  Yehezkel Friedman ,  Zeev Heller

发明人： Michal Schramm ,  Ziv Hershman ,  Yehezkel Friedman ,  Zeev Heller

IPC分类号： G06F1/32

CPC分类号： G06F13/385 ,  Y02D10/14 ,  Y02D10/151

摘要： Universal serial bus wakeup when the bus is not powered. In one embodiment, a method of waking up a universal serial bus (USB) from a non-powered state, comprises: upon detection of a wakeup condition, a wakeup generation module associated with a USB device generating a wakeup signal on a power line of a USB bus coupled to the USB device, or on a single-wire sideband; and a host wakeup module detecting the wakeup signal and causing the USB bus that is coupled to the USB device to be supplied with power.

摘要翻译： 总线未通电时通用串行总线唤醒。 在一个实施例中，一种从非供电状态唤醒通用串行总线（USB）的方法包括：在检测到唤醒条件时，与USB设备相关联的唤醒生成模块在生成唤醒条件的电力线上产生唤醒信号 耦合到USB设备的USB总线或单线边带上的USB总线; 以及主机唤醒模块，其检测所述唤醒信号并且使与所述USB设备耦合的所述USB总线被供电。

公开(公告)号：US07890726B1

公开(公告)日：2011-02-15

申请号：US11894977

申请日：2007-08-22

申请人： Ohad Falik ,  Michal Schramm

发明人： Ohad Falik ,  Michal Schramm

IPC分类号： G06F12/00

CPC分类号： G06F13/1605 ,  G06F8/654 ,  G06F12/1425

摘要： An apparatus and method are disclosed. The apparatus allows dynamic setting of access permissions to contents of a shared memory in a memory device controlled by an embedded controller and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via an arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the shared memory.

摘要翻译： 公开了一种装置和方法。 该装置允许对由嵌入式控制器控制的存储器件中的共享存储器的内容的访问许可权的动态设置，并允许更新和恢复内容。 包括至少一个与存储器件连接的主机的计算机化系统提供到共享存储器，主机和嵌入式控制器的访问路径。 存储器件被分割成单独的块，每个块用于存储不同类型的数据。 在共享存储器中指定一个位置，用于存储保护信息，该保护信息包括与由共享存储器的一部分的至少一个访问路径允许的访问操作有关的数据。 通过使用访问控制单元允许/禁止访问共享存储器的预定部分，通过仲裁设备访问共享存储器的单独部分。

公开(公告)号：US07508257B2

公开(公告)日：2009-03-24

申请号：US11517127

申请日：2006-09-06

申请人： Victor Flachs ,  Michal Schramm ,  Ilan Margalit

发明人： Victor Flachs ,  Michal Schramm ,  Ilan Margalit

IPC分类号： H03K9/00

CPC分类号： H04B10/1141

摘要： Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

摘要翻译： 用于解调脉冲序列的装置包括具有异步数据输入端子的单触发器件，其被配置为接收脉冲串，以及单触发数据输出端子。 第一时钟逻辑门具有耦合到单触发数据输出端的第一时钟数据输入端和第一时钟数据输出端。 组合逻辑门具有耦合到单触发和第一时钟数据输出端的组合输入端和组合输出端。 第二时钟逻辑门具有耦合到组合输出端的第二时钟数据输入端和被配置为输出脉冲序列的解调包络的第二时钟数据输出端。

公开(公告)号：US20080075471A1

公开(公告)日：2008-03-27

申请号：US11517127

申请日：2006-09-06

申请人： Victor Flachs ,  Michal Schramm ,  Ilan Margalit

发明人： Victor Flachs ,  Michal Schramm ,  Ilan Margalit

IPC分类号： H04B10/06

CPC分类号： H04B10/1141

摘要： Apparatus for demodulating a train of pulses includes a one-shot device having an asynchronous data input terminal, which is configured to receive the train of pulses, and a one-shot data output terminal. A first clocked logic gate has a first clocked data input terminal, which is coupled to the one-shot data output terminal, and a first clocked data output terminal. A combinatorial logic gate has combinatorial input terminals, which are coupled to the one-shot and first clocked data output terminals, and a combinatorial output terminal. A second clocked logic gate has a second clocked data input terminal, which is coupled to the combinatorial output terminal, and a second clocked data output terminal, which is configured to output a demodulated envelope of the train of pulses.

摘要翻译： 用于解调脉冲序列的装置包括具有异步数据输入端子的单触发器件，其被配置为接收脉冲串，以及单触发数据输出端子。 第一时钟逻辑门具有耦合到单触发数据输出端的第一时钟数据输入端和第一时钟数据输出端。 组合逻辑门具有耦合到单触发和第一时钟数据输出端的组合输入端和组合输出端。 第二时钟逻辑门具有耦合到组合输出端的第二时钟数据输入端和被配置为输出脉冲序列的解调包络的第二时钟数据输出端。

公开(公告)号：US07318129B1

公开(公告)日：2008-01-08

申请号：US11301287

申请日：2005-12-12

申请人： Ohad Falik ,  Michal Schramm

发明人： Ohad Falik ,  Michal Schramm

IPC分类号： G06F12/14

CPC分类号： G06F13/1605 ,  G06F8/654 ,  G06F12/1425

摘要： An apparatus and method are disclosed for protecting the contents of a shared memory in a memory device controlled by an embedded controller. The apparatus allows dynamic setting of access permissions to said contents and allows updating and recovery of the contents. A computerized system comprising at least one Host linked to the memory device provides access paths to the shared memory, to the Host, and to the embedded controller. An arbitration device for allocating access paths to the memory device is also provided. The memory device is partitioned into separate blocks, each of which is used to store different types of data. A location is designated in the shared memory for storing protection information that includes data related to access operations allowed by at least one access path to a part of the shared memory. Access, via the arbitration device, to separate parts of the shared memory is permitted by using an access control unit that enables/disables access to predetermined portions of the hared memory by at least one of the access paths.

摘要翻译： 公开了一种用于保护由嵌入式控制器控制的存储器件中的共享存储器的内容的装置和方法。 该装置允许对所述内容的访问权限的动态设置，并且允许更新和恢复内容。 包括至少一个与存储器件连接的主机的计算机化系统提供到共享存储器，主机和嵌入式控制器的访问路径。 还提供了一种用于向存储设备分配访问路径的仲裁设备。 存储器件被分割成单独的块，每个块用于存储不同类型的数据。 在共享存储器中指定一个位置，用于存储保护信息，该保护信息包括与由共享存储器的一部分的至少一个访问路径允许的访问操作有关的数据。 通过使用访问控制单元来允许通过仲裁设备访问共享存储器的单独部分，该访问控制单元能够通过至少一个访问路径来启用/禁用访问已存储的存储器的预定部分。

公开(公告)号：US08688944B2

公开(公告)日：2014-04-01

申请号：US13236673

申请日：2011-09-20

申请人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

发明人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1663 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.

摘要翻译： 嵌入式控制器包括微控制器核心和存储器控制电路。 存储器控制电路经配置以通过第一串行外设接口（SPI）与第一串行外设接口（SPI）进行通信，对于该第一串行外设接口（SPI），不支持总线仲裁，以第一时钟速率通过第二SPI与存储器进行通信 以第二固定时钟速率，通过第一和第二SPI来中继​​CPU芯片组和存储器之间的存储器事务，以识别在第二SPI上没有存储器事务中继的时间间隔，并且从存储器检索用于操作的信息 在确定的时间间隔内的微控制器内核。

公开(公告)号：US20120239848A1

公开(公告)日：2012-09-20

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。

公开(公告)号：US08285895B2

公开(公告)日：2012-10-09

申请号：US11834053

申请日：2007-08-06

申请人： Michal Schramm ,  Nir Tasher

发明人： Michal Schramm ,  Nir Tasher

IPC分类号： G06F3/00

CPC分类号： G06F13/1663 ,  G06F13/24

摘要： A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.

摘要翻译： 一种系统装置，包括存储单元，该存储器单元具有根据存储器和访问主机之间的无握手协议的存储器接口，连接到存储器单元的总线以及第一和第二主控器。 第一个主机通过总线和存储器接口来操作存储器单元，并且通过中断接口接收到中断请求后执行中断。 第二台主机通过总线和存储器接口操作存取存储单元。 第二主控器被配置为在访问存储器单元之前将中断请求传送到第一处理器。