公开(公告)号：US20090152626A1

公开(公告)日：2009-06-18

申请号：US11959032

申请日：2007-12-18

Applicant: Ramesh Venugopal ,  Srinivasan Chakravarthi ,  Chris Bowen

Inventor： Ramesh Venugopal ,  Srinivasan Chakravarthi ,  Chris Bowen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814

Abstract: Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.

Abstract translation: 集成电路中MOS晶体管的收缩尺寸需要从光晕离子注入工艺在口袋区域中更严格地分配掺杂剂。 在常规制造工艺序列中，卤素掺杂剂分布在源极/漏极退火期间扩散。 本发明是在源极/漏极退火之后执行卤素离子的集成电路中制造MOS晶体管的方法。 在本发明的方法中，在卤素离子注入工艺之前，MOS栅极侧壁上的源极/漏极间隔物被去除。 偏移金属硅化物的间隔物在晕轮植入物之后形成，并且可以是低k电介质材料以减小栅极至漏极电容。 在源极/漏极间隔物被去除之后，压电应力层可以沉积在MOS栅极上，以提高MOS栅极的应力传递效率。 还公开了体现本发明方法的集成电路。

公开(公告)号：US20060223248A1

公开(公告)日：2006-10-05

申请号：US11091989

申请日：2005-03-29

Applicant: Ramesh Venugopal ,  Christoph Wasshuber ,  David Scott

Inventor： Ramesh Venugopal ,  Christoph Wasshuber ,  David Scott

IPC: H01L21/336

CPC classification number: H01L29/7838 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/517

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract translation: 本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。 通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。 在器件（300）上形成高k电介质层（308）。 在高k电介质层上形成多晶硅层（310），并掺杂n型。 图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。

公开(公告)号：US20110175168A1

公开(公告)日：2011-07-21

申请号：US12538468

申请日：2009-08-10

Applicant: Xin WANG ,  Zhiqiang WU ,  Ramesh VENUGOPAL

Inventor： Xin WANG ,  Zhiqiang WU ,  Ramesh VENUGOPAL

IPC: H01L27/092 ,  H01L29/772 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7847

Abstract: A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Abstract translation: 公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。 栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成 金属硅化物。 用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。 多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

公开(公告)号：US07407850B2

公开(公告)日：2008-08-05

申请号：US11091989

申请日：2005-03-29

Applicant: Ramesh Venugopal ,  Christoph Wasshuber ,  David Barry Scott

Inventor： Ramesh Venugopal ,  Christoph Wasshuber ,  David Barry Scott

IPC: H01L21/8238

CPC classification number: H01L29/7838 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/517

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract translation: 本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。 通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。 在器件（300）上形成高k电介质层（308）。 在高k电介质层上形成多晶硅层（310），并掺杂n型。 图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。

公开(公告)号：US07208379B2

公开(公告)日：2007-04-24

申请号：US10997936

申请日：2004-11-29

Applicant: Ramesh Venugopal ,  Christoph Wasshuber

Inventor： Ramesh Venugopal ,  Christoph Wasshuber

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/8086

Abstract: A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.

Abstract translation: 公开了一种用于乘以半导体器件的间距的方法。 该方法包括在第一层上形成图案化掩模层，其中图案化掩模层具有第一线宽度。 然后可以蚀刻第一层以形成第一多个倾斜的侧壁。 在去除图案化掩模的一部分以使得图案化掩模层具有小于第一线宽度的第二线宽度之后，可以再次蚀刻第一层以形成第二多个倾斜侧壁。 然后可以去除图案化的掩模层。 可以再次蚀刻第一层以形成第三多个倾斜的侧壁。 第一多个倾斜侧壁，第二多个倾斜侧壁和第三多个倾斜侧壁可以形成平行三角形通道的阵列。

公开(公告)号：US20120190158A1

公开(公告)日：2012-07-26

申请号：US13440344

申请日：2012-04-05

Applicant: Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

Inventor： Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7847

Abstract: A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Abstract translation: 公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。 栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成 金属硅化物。 用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。 多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

公开(公告)号：US20060113636A1

公开(公告)日：2006-06-01

申请号：US10997936

申请日：2004-11-29

Applicant: Ramesh Venugopal ,  Christoph Wasshuber

Inventor： Ramesh Venugopal ,  Christoph Wasshuber

IPC: H01L29/06 ,  H01L21/467

CPC classification number: H01L21/28123 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/78696 ,  H01L29/808 ,  H01L29/8086

Abstract: A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels.

Abstract translation: 公开了一种用于乘以半导体器件的间距的方法。 该方法包括在第一层上形成图案化掩模层，其中图案化掩模层具有第一线宽度。 然后可以蚀刻第一层以形成第一多个倾斜的侧壁。 在去除图案化掩模的一部分以使得图案化掩模层具有小于第一线宽度的第二线宽度之后，可以再次蚀刻第一层以形成第二多个倾斜侧壁。 然后可以去除图案化的掩模层。 可以再次蚀刻第一层以形成第三多个倾斜的侧壁。 第一多个倾斜侧壁，第二多个倾斜侧壁和第三多个倾斜侧壁可以形成平行三角形通道的阵列。

公开(公告)号：US08435849B2

公开(公告)日：2013-05-07

申请号：US13440344

申请日：2012-04-05

Applicant: Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

Inventor： Xin Wang ,  Zhiqiang Wu ,  Ramesh Venugopal

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7845 ,  H01L29/7847

Abstract: A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.

Abstract translation: 公开了用于在NMOS沟道中引起拉伸应力的IC中的NMOS晶体管的栅极堆叠。 栅极堆叠包括第一层未掺杂的多晶硅，第二层n型多晶硅，以在栅极中建立所需的功函数，压缩应力金属层，以及第三层多晶硅，以提供硅表面，用于随后形成 金属硅化物。 用于压应力金属的候选物是TiN，TaN，W和Mo。在CMOS IC中，n型多晶硅层和金属层在NMOS晶体管区域中被图案化，而第一多晶硅层和第三多晶硅层被图案化 NMOS和PMOS晶体管区域。 多晶硅CMP可以用于减小NMOS和PMOS栅极堆叠之间的形貌，以便于栅极图案光刻。

公开(公告)号：US20090050980A1

公开(公告)日：2009-02-26

申请号：US11842242

申请日：2007-08-21

Applicant: Shashank S. EKBOTE ,  Srinivasan CHAKRAVARTHI ,  Ramesh VENUGOPAL

Inventor： Shashank S. EKBOTE ,  Srinivasan CHAKRAVARTHI ,  Ramesh VENUGOPAL

IPC: H01L29/94 ,  H01L21/425

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor device with source/drain nitrogen implant, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a substrate, implanting a dopant species into an active region adjacent to the gate stack, and reducing a diffusivity of the dopant species by implanting nitrogen into the active region.

Abstract translation: 一种形成具有源极/漏极氮植入物的半导体器件的方法及相关器件。 示例性实施例中的至少一些是包括在衬底上形成栅极堆叠的方法，将掺杂剂物质注入到与栅极堆叠相邻的有源区域中，以及通过将氮注入到有源区域来降低掺杂剂物质的扩散率。

公开(公告)号：US20080272442A1

公开(公告)日：2008-11-06

申请号：US12137674

申请日：2008-06-12

Applicant: Ramesh Venugopal ,  Christoph Wasshuber ,  David Barry Scott

Inventor： Ramesh Venugopal ,  Christoph Wasshuber ,  David Barry Scott

IPC: H01L29/78

CPC classification number: H01L29/7838 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/517

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).

Abstract translation: 本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。 通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。 在器件（300）上形成高k电介质层（308）。 在高k电介质层上形成多晶硅层（310），并掺杂n型。 图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。