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公开(公告)号：US08504972B2
公开(公告)日：2013-08-06
申请号：US12697887
申请日：2010-02-01
申请人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
发明人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
摘要翻译： 集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。 第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。
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公开(公告)号：US20100269081A1
公开(公告)日：2010-10-21
申请号：US12697887
申请日：2010-02-01
申请人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
发明人： Yung-Chin Hou , David Barry Scott , Lee-Chung Lu , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.
摘要翻译： 集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。 第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。
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3.发明授权Design method and system for optimum performance in integrated circuits that use power management 有权使用电源管理的集成电路中的最佳性能设计方法和系统公开(公告)号：US07216310B2
公开(公告)日：2007-05-08
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Barry Scott , Theodore W. Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译： 本发明提供一种设计电路的方法（100）。 该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。 所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。 使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。 该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。
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公开(公告)号：US20120123745A1
公开(公告)日：2012-05-17
申请号：US12947016
申请日：2010-11-16
CPC分类号： G06F17/5036 , G06F2217/76
摘要： A system and method for simulating aging parameters of a System-on-Chip (SoC) integrated circuit is disclosed. A SoC integrated circuit is first divided into a plurality of blocks in accordance with the nature or the operating conditions of each block. The simulation of a digital circuit based block is performed by a static timing analyzer. The simulation of a mixed signal based block is performed by first employing a fresh device model to obtain relevant operation conditions, such as node voltages. Based upon the operation conditions and reliability characterization data, parameters degradation calculators assess aging characteristic factors of each block. In a subsequent simulation, a circuit simulator calculates the design corners of a SoC chip based upon the characteristic factors of each block.
摘要翻译： 公开了一种用于模拟片上系统（SoC）集成电路的老化参数的系统和方法。 根据每个块的性质或操作条件，首先将SoC集成电路分为多个块。 基于数字电路的块的仿真由静态时序分析器执行。 基于混合信号的块的模拟通过首先采用新的设备模型来获得诸如节点电压的相关操作条件来进行。 根据操作条件和可靠性特征数据，参数退化计算器评估每个块的老化特征因子。 在随后的仿真中，电路仿真器基于每个块的特征因子来计算SoC芯片的设计角。
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公开(公告)号：US07236396B2
公开(公告)日：2007-06-26
申请号：US11171033
申请日：2005-06-30
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.
摘要翻译： 具有虚拟单元行结构的SRAM阵列，其中SRAM阵列被划分成由虚设单元的行图案隔离的段。 虚拟单元结构在较低单元图案化水平下提供连续的单元阵列。 SRAM阵列包括第一和第二阵列块，每个第一和第二阵列块包括具有第一布局配置的SRAM单元，一个或多个虚拟单元具有沿着与SRAM阵列的字线相关联的行图案布置的第二布局配置，第一功率 连接到第一阵列块的电源电压线和连接到第二阵列块的第二不同电源电压线。 阵列块的第一和第二电源电压线还连接到一个或多个虚设单元。
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公开(公告)号：US20120032518A1
公开(公告)日：2012-02-09
申请号：US12851023
申请日：2010-08-05
IPC分类号： H02J1/10
CPC分类号： H02J7/35 , H02J1/10 , H02J7/0055 , H02J7/025 , H02J17/00 , H02J50/00 , H02J50/20 , H02J50/30 , H02J50/40 , Y10T307/702
摘要： An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.
摘要翻译： 能量收集系统包括多个换能器。 传感器被配置为从多个环境能量源产生直流（DC）电压。 传感器控制电路具有被配置为检测来自多个换能器的直流信号的多个传感器。 DC-DC转换器被配置为提供输出电压。 多个开关，每个开关耦合在DC-DC转换器和多个换能器中的相应换能器之间。 传感器控制电路使得多个开关中的一个开关能够基于优先级标准而禁用多个开关中的其它开关。
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公开(公告)号：US20080272442A1
公开(公告)日：2008-11-06
申请号：US12137674
申请日：2008-06-12
IPC分类号： H01L29/78
CPC分类号： H01L29/7838 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823857 , H01L29/517
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
摘要翻译： 本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。 通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。 在器件（300）上形成高k电介质层（308）。 在高k电介质层上形成多晶硅层（310），并掺杂n型。 图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。
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公开(公告)号：US20110153055A1
公开(公告)日：2011-06-23
申请号：US12640398
申请日：2009-12-17
CPC分类号： G06F17/5036
摘要： A method includes selecting one of a plurality of existing transistor models for which fabrication and performance data are available, receiving first model data for a next-generation transistor based on target response data and the selected transistor model data, and simulating a response of a circuit including the next-generation transistor. The selection of the existing transistor model is based on target response data for the next-generation transistor for which fabrication and performance data are not available. The simulation is performed using the first transistor model data for the next-generation transistor. A difference between the target response and the simulated response of the next-generation transistor is calculated, and the first model data representing the next-generation transistor is stored in a computer readable storage medium if the performance data difference between the target response and the simulated response is below a threshold.
摘要翻译： 一种方法包括选择制造和性能数据可用的多个现有晶体管模型中的一个，基于目标响应数据和所选择的晶体管模型数据接收用于下一代晶体管的第一模型数据，以及模拟电路的响应 包括下一代晶体管。 现有晶体管模型的选择是基于制造和性能数据不可用的下一代晶体管的目标响应数据。 使用下一代晶体管的第一晶体管模型数据进行模拟。 计算下一代晶体管的目标响应和模拟响应之间的差异，并且表示下一代晶体管的第一模型数据被存储在计算机可读存储介质中，如果目标响应与模拟的 响应低于阈值。
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公开(公告)号：US08432071B2
公开(公告)日：2013-04-30
申请号：US12851023
申请日：2010-08-05
IPC分类号： G05F3/06
CPC分类号： H02J7/35 , H02J1/10 , H02J7/0055 , H02J7/025 , H02J17/00 , H02J50/00 , H02J50/20 , H02J50/30 , H02J50/40 , Y10T307/702
摘要： An energy harvesting system includes a plurality of transducers. The transducers are configured to generate direct current (DC) voltages from a plurality of ambient energy sources. A sensor control circuit has a plurality of sensors configured to detect the DC signals from the plurality of transducers. A DC-to-DC converter is configured to supply an output voltage. A plurality of switches, each switch coupled between the DC-to-DC converter and a corresponding transducer of the plurality of transducers. The sensor control circuit enables one switch of the plurality of switches and disables the other switches of the plurality of switches based on a priority criterion.
摘要翻译： 能量收集系统包括多个换能器。 传感器被配置为从多个环境能量源产生直流（DC）电压。 传感器控制电路具有被配置为检测来自多个换能器的直流信号的多个传感器。 DC-DC转换器被配置为提供输出电压。 多个开关，每个开关耦合在DC-DC转换器和多个换能器中的相应换能器之间。 传感器控制电路使得多个开关中的一个开关能够基于优先级标准而禁用多个开关中的其它开关。
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公开(公告)号：US07407850B2
公开(公告)日：2008-08-05
申请号：US11091989
申请日：2005-03-29
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823857 , H01L29/517
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that employ high-k dielectric layers. An n-type well region (304) is formed within a semiconductor body (302). A threshold voltage adjustment implant is performed by implanting a p-type dopant into the n-type well region to form a counter doped region (307). A high-k dielectric layer (308) is formed over the device (300). A polysilicon layer (310) is formed on the high-k dielectric layer and doped n-type. The high-k dielectric layer (308) and the polysilicon layer (310) are patterned to form polysilicon gate structures. P-type source/drain regions (306) are formed within the n-type well region (304).
摘要翻译： 本发明通过提供采用高k电介质层的制造方法来促进半导体制造。 n型阱区（304）形成在半导体本体（302）内。 通过将p型掺杂剂注入到n型阱区域中以形成反掺杂区域（307）来执行阈值电压调整注入。 在器件（300）上形成高k电介质层（308）。 在高k电介质层上形成多晶硅层（310），并掺杂n型。 图案化高k电介质层（308）和多晶硅层（310）以形成多晶硅栅极结构。 P型源极/漏极区（306）形成在n型阱区（304）内。
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