摘要:
An athlete recruiting network in which athletes create athlete profiles that are stored within an athlete module of a recruiting database. One or more coaches use coach interfaces to create coaching rosters that are stored within a coach module within the recruiting database. The athlete interfaces and the coach interfaces include computers, laptops, telephones and other forms of remote terminals that are wired or wirelessly connected to the database. The athlete recruiting network allows coaches to search for one or more athletes based on desired characteristics such as athletic statistics, the athlete's position or particular skills, the athlete's academic achievements, and other criteria designated by the coach. Further, the athlete-recruiting network allows the athletes to promote their particular skills or abilities to coaches searching for athletes to complete the coach's roster.
摘要:
The present invention is a phase dithered digital communications system that includes a digital receiver, and uses phase dithering to spread the energy of one or more system clocks to minimize receiver de-sensitization. Phase dithering uses a single frequency for each system clock; however, the energy of each system clock is spread over a range of frequencies by changing the duty-cycle of each clock half-cycle. A non-phase dithered clock drives the sampling clock of a receiver analog-to-digital converter to provide accurate correlation with received information, which may allow use of a higher frequency sampling clock than in frequency dithered designs. Phase dithered clocks and non-phase dithered clocks may have constant frequencies that are related to each other by a ratio of two integers; therefore, the time base used for extracting received data is always correlated and accurate.
摘要:
A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.
摘要:
A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.
摘要:
The present invention provides an MHC class II antigen presentation enhancing hybrid polypeptide. The hybrid has an N-terminus comprising the mammalian Ii key peptide LRMKLPKPPKPVSKMR (SEQ ID NO: 1) and modifications thereof which retain antigen presentation enhancing activity, a C-terminus comprising an antigenic epitope in the form of a polypeptide or peptidomimetic structure which binds to the antigenic peptide binding site of an MHC class II molecule, and an intervening chemical structure covalently linking the N-terminal and C-terminal components.
摘要翻译:本发明提供了增强MHC II类抗原呈递的杂交多肽。 杂合体具有包含哺乳动物Ii关键肽LRMKLPKPPKPVSKMR(SEQ ID NO:1)的N末端及其保留抗原呈递增强活性的修饰,C末端包含多肽形式的抗原表位或肽模拟结构,其结合 涉及MHC II类分子的抗原肽结合位点,以及共价连接N-末端和C-末端组分的中间化学结构。
摘要:
The invention provides an apparatus and method for calibrating both the pole/zero locations and the gain of a charge pump phase-locked loop's (PLL's) frequency response with one calibration operation. In one embodiment, the calibration is performed using a bandgap voltage reference and a stable frequency reference in order to measure a slew rate (I/C), defined as a current-to-capacitance ratio, and then adjusting the RC time constant (tRC) by adjusting the capacitance value. The adjustment setting is used in the loop filter capacitors, thereby calibrating the pole and zero locations of the PLL, which depend on the RC product. The charge pump reference current is proportional to the ratio of the bandgap voltage to the resistor value. When the capacitance is adjusted, the slew rate is calibrated as well, wherein the slew rate represents a portion of the loop gain of the PLL.
摘要:
The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a divided reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.
摘要:
A selective call radio (300) includes receiver (200). The receiver in turn includes an antenna (202) for receiving a radio signal having a first operating frequency, an amplifier(204) coupled thereto for generating an amplified signal; and a frequency translation circuit (208). The frequency translation circuit includes a selectivity filter (212) and an integrated frequency conversion circuit (216). The selectivity is coupled to the amplified signal for generating a filtered signal. The integrated frequency conversion circuit is coupled to the filtered signal and is incorporated into at least one IC (integrated circuit). The integrated frequency conversion circuit includes an oscillator (220), a divider (224), and a mixer (218). A first input of the mixer is coupled to the filtered signal generated by the selectivity filter. The divider is coupled to the oscillator and its output is coupled to a second input of the mixer. The mixer generates an output signal having a second operating frequency, the second operating frequency having a frequency value different from the frequency value of the first operating frequency of the radio signal.