公开(公告)号：US07412215B1

公开(公告)日：2008-08-12

申请号：US11144119

申请日：2005-06-03

申请人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz ,  Scott Robert Humphreys

发明人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz ,  Scott Robert Humphreys

IPC分类号： H04B1/04

CPC分类号： H04B1/0475 ,  H03L7/081 ,  H03L7/087 ,  H03L7/16 ,  H03L2207/12

摘要： A system and method are provided for switching from one phase-locked loop feedback source to another in a radio frequency (RF) transmitter. The RF transmitter includes a phase-locked loop (PLL) that provides a phase-modulated RF input signal and power amplifier circuitry that amplifies the RF input signal to provide an RF output signal. The PLL includes switching circuitry that couples a feedback path of the PLL to an output of the PLL for open loop operation and couples the feedback path of the PLL to an output of the power amplifier circuitry for closed loop operation. Prior to switching the feedback path from the output of the PLL to the output of the power amplifier circuitry, time alignment circuitry operates to time-align feedback signals from the outputs of the PLL and the power amplifier circuitry such that switching from open loop operation to closed loop operation causes minimal phase disturbance.

摘要翻译： 提供了一种用于在射频（RF）发射机中从一个锁相环反馈源切换到另一个的系统和方法。 RF发射器包括提供相位调制RF输入信号的锁相环（PLL）和放大RF输入信号以提供RF输出信号的功率放大器电路。 PLL包括将PLL的反馈路径耦合到PLL的输出以用于开环操作的开关电路，并将PLL的反馈路径耦合到用于闭环操作的功率放大器电路的输出。 在将反馈路径从PLL的输出切换到功率放大器电路的输出之前，时间对准电路用于对来自PLL和功率放大器电路的输出的反馈信号进行时间对准，使得从开环操作切换到 闭环运行导致最小的相位扰动。

公开(公告)号：US08463209B1

公开(公告)日：2013-06-11

申请号：US12843672

申请日：2010-07-26

申请人： Michael R. Kay ,  Alexander Wayne Hietala ,  Jeffery Peter Ortiz

发明人： Michael R. Kay ,  Alexander Wayne Hietala ,  Jeffery Peter Ortiz

IPC分类号： H04B1/04

CPC分类号： H03G3/3047 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/207 ,  H03F2200/465

摘要： The described devices, systems and methods include an integrator circuit having two separate operational modes to control a power output level delivered by the power amplifier to an antenna during start of a transmission burst. The first operational mode utilizes a wide bandwidth control loop to pre-charge a capacitor of the integrator circuit, which generates a pedestal voltage delivered to the power amplifier control input. The second operational mode utilizes a lower bandwidth control loop to ensure stable operation of the control loop during normal operation of the power amplifier.

摘要翻译： 所描述的器件，系统和方法包括具有两个单独操作模式的积分器电路，以在发射突发开始期间控制由功率放大器传送到天线的功率输出电平。 第一种操作模式利用宽带宽控制环来对积分器电路的电容器进行预充电，该电容器产生传递到功率放大器控制输入端的基座电压。 第二种操作模式利用较低带宽控制回路来确保在功率放大器正常工作期间控制回路的稳定运行。

公开(公告)号：US08874050B1

公开(公告)日：2014-10-28

申请号：US12774155

申请日：2010-05-05

申请人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz ,  Timothy Keith Coffman

发明人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz ,  Timothy Keith Coffman

IPC分类号： H01Q11/12

CPC分类号： H01P5/184 ,  H03F1/0211 ,  H03F3/195 ,  H03F3/24 ,  H03F3/68 ,  H03F2200/541 ,  H03H7/38

摘要： A circuit and method for a saturation correction of a power amplifier (PA) is provided in order to maintain a desirable switching spectrum. The circuit includes a closed loop system that is responsive to a dynamic PA control signal known as VRAMP. The method samples a detector voltage that represents the output of the PA at the maximum voltage level of VRAMP. The sampled detector voltage is then reduced by a predetermined amount and applied as a fixed voltage PA control signal in the place of VRAMP. As a result, the closed loop system responds to the fixed voltage PA control signal to bring the PA out of saturation before VRAMP can begin a voltage decrease. Once the VRAMP voltage decreases, VRAMP is reapplied as a dynamic PA control signal in place of the fixed voltage control signal.

摘要翻译： 提供了用于功率放大器（PA）的饱和校正的电路和方法，以便保持期望的开关频谱。 电路包括响应于称为VRAMP的动态PA控制信号的闭环系统。 该方法对在VRAMP的最大电压电平下表示PA输出的检测器电压进行采样。 然后将取样的检测器电压减小预定量并作为固定电压PA控制信号施加在VRAMP的位置。 结果，闭环系统响应于固定电压PA控制信号，使得在VRAMP可以开始降压之前使PA失去饱和。 一旦VRAMP电压降低，VRAMP将重新应用为动态PA控制信号，代替固定电压控制信号。

公开(公告)号：US08193859B1

公开(公告)日：2012-06-05

申请号：US12882313

申请日：2010-09-15

申请人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz

发明人： Alexander Wayne Hietala ,  Jeffery Peter Ortiz

IPC分类号： H03G3/20

CPC分类号： H03G3/3042

摘要： A dual FET detector having a common RF input and a common detector output for two detector circuits is provided. The first detector circuit is optimized for detecting lower RF signal levels while the second detector circuit is optimized for detecting higher RF signal levels. A detector output voltage output from the common detector output is a composite signal made up of the individual contributions of the two detector circuits. A control circuit receives a feedback signal derived from the detector output voltage, and uses the feedback signal to control a transition between urging a predominance of the contribution to the detector output voltage from one of the detector circuits to the other. The control of the transition between the detector circuits ensures that whichever of the two detector circuits is best optimized for a particular RF signal level will contribute the most to the detector output voltage.

摘要翻译： 提供具有公共RF输入和用于两个检测器电路的公共检测器输出的双FET检测器。 第一检测器电路被优化用于检测较低的RF信号电平，而第二检测器电路被优化用于检测更高的RF信号电平。 从公共检测器输出输出的检测器输出电压是由两个检测器电路的各自贡献组成的复合信号。 控制电路接收从检测器输出电压导出的反馈信号，并且使用反馈信号来控制在从检测器电路之一到检测器电路之间的对检测器输出电压的贡献的主导之间的转变。 对检测器电路之间的转换的控制确保两个检测器电路中的任一个针对特定的RF信号电平进行最佳优化，将对检测器的输出电压贡献最大。