Control device, for instance for systems-on-chip, and corresponding method
    1.
    发明授权
    Control device, for instance for systems-on-chip, and corresponding method 有权
    控制装置,例如片上系统以及相应的方法

    公开(公告)号:US09100354B2

    公开(公告)日:2015-08-04

    申请号:US13690109

    申请日:2012-11-30

    CPC classification number: H04L47/783 H04L47/52 H04L49/109

    Abstract: A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.

    Abstract translation: 系统包括诸如片上网络(NoC)类型的诸如互连的资源,具有可用于分配给竞争总体带宽分配的一组发起者的总带宽。 该系统包括通信仲裁器,用于根据发起者所请求的带宽(RBW)的相应值将总带宽分配给发起者。 控制装置(50)被配置为检测分配给发起者的带宽值与所请求带宽的相应值之间的偏差,并以动态方式将总体带宽分配给发起者,以使偏差的平均值最小化。

    METHOD FOR REGULATING DATA TRANSMISSION OVER A COMMUNICATION CHANNEL, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT
    2.
    发明申请
    METHOD FOR REGULATING DATA TRANSMISSION OVER A COMMUNICATION CHANNEL, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT 有权
    用于调整通信信道,对应设备和计算机程序产品的数据传输的方法

    公开(公告)号:US20140140354A1

    公开(公告)日:2014-05-22

    申请号:US14067811

    申请日:2013-10-30

    CPC classification number: H04L12/413 H04J3/16 H04L27/18

    Abstract: Transmission of data frames over a channel in a communications network takes place on a slotted time base. A method comprises an evaluation, by at at least one node of the network having a frame available for transmission, of whether the channel is available for transmission. If the the channel is available for transmission, the available frame is transmitted over the channel in a subsequent slot of the slotted time base. If the channel is not available for transmission, owing to a frame (having a certain temporal length) being transmitted over the channel at a certain time, the slotted time base of the at least one node is resynchronized as a function of the frame being transmitted. The resynchronization includes identifying, as a function of the certain temporal length, an interval of delay to evaluate again in at a furture time whether the channel is available for transmission.

    Abstract translation: 在通信网络中的信道上的数据帧的传输在时隙基础上进行。 一种方法包括在具有可用于传输的帧的网络的至少一个节点处评估该信道是否可用于传输。 如果信道可用于传输,则可用帧在时隙时基的后续时隙中通过信道发送。 如果信道不可用于传输,则由于在特定时间通过信道发送帧(具有一定的时间长度),所述至少一个节点的时隙时基被重新同步为正被发送的帧的函数 。 重新同步包括根据特定时间长度来识别延迟的时间间隔,以在频道是否可用于传输的情况下再次进行评估。

    GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER
    4.
    发明申请
    GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER 审中-公开
    GOP独立动态位速率控制器

    公开(公告)号:US20130202031A1

    公开(公告)日:2013-08-08

    申请号:US13827210

    申请日:2013-03-14

    Abstract: A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.

    Abstract translation: 独立于GOP的动态比特率控制器系统包括用于接收一个或多个输入参数的用户界面,比特率控制器和编码器。 比特率控制器调节输出比特流的比特率。 比特率控制器包括用于确定比特估计和量化参数的多个比特率模块,以及基于所接收的输入参数和帧速率来计算收敛周期的控制模块。 控制模块基于收敛周期选择比特率模块,并且编码器使用由比特率模块确定的量化参数来生成输出比特流。

    CONTROL DEVICE, FOR INSTANCE FOR SYSTEMS-ON-CHIP, AND CORRESPONDING METHOD
    6.
    发明申请
    CONTROL DEVICE, FOR INSTANCE FOR SYSTEMS-ON-CHIP, AND CORRESPONDING METHOD 有权
    控制装置,用于实现系统中的芯片以及相应的方法

    公开(公告)号:US20130163615A1

    公开(公告)日:2013-06-27

    申请号:US13690109

    申请日:2012-11-30

    CPC classification number: H04L47/783 H04L47/52 H04L49/109

    Abstract: A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.

    Abstract translation: 系统包括诸如片上网络(NoC)类型的诸如互连的资源,具有可用于分配给竞争总体带宽分配的一组发起者的总带宽。 该系统包括通信仲裁器,用于根据发起者所请求的带宽(RBW)的相应值将总带宽分配给发起者。 控制装置(50)被配置为检测分配给发起者的带宽值与所请求带宽的相应值之间的偏差,并以动态方式将总体带宽分配给发起者,以使偏差的平均值最小化。

    ANALOG TO DIGITAL CONVERSION APPARATUS WITH A REDUCED NUMBER OF ADCs
    8.
    发明申请
    ANALOG TO DIGITAL CONVERSION APPARATUS WITH A REDUCED NUMBER OF ADCs 有权
    模拟数字转换设备与减少的ADC数

    公开(公告)号:US20140043180A1

    公开(公告)日:2014-02-13

    申请号:US14055874

    申请日:2013-10-16

    CPC classification number: H03M1/122

    Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

    Abstract translation: 模数转换器包括用于接收模拟输入信号的多路复用器电路,并且响应于选择输入,模数转换器电路将所选择的模拟信号转换成数字信号,转换启动装置将转换开始信号发送到 触发事件的基础,转换启动装置响应于选择输入,定序器,用于控制模数转换器电路,以基于一个转换顺序指令执行一个序列转换;以及FIFO寄存器块,用于接收转换 序列指令,并且如果实际转换序列正在进行,并且能够对每个新的接收到的转换序列指令进行排队,并且在执行转换序列之后控制定序器执行新的序列转换指令。

    Method for regulating data transmission over a communication channel, corresponding device and computer program product
    9.
    发明授权
    Method for regulating data transmission over a communication channel, corresponding device and computer program product 有权
    通过通信通道调节数据传输的方法,相应的设备和计算机程序产品

    公开(公告)号:US09258139B2

    公开(公告)日:2016-02-09

    申请号:US14067811

    申请日:2013-10-30

    CPC classification number: H04L12/413 H04J3/16 H04L27/18

    Abstract: Transmission of data frames over a channel in a communications network takes place on a slotted time base. A method comprises an evaluation, by at least one node of the network having a frame available for transmission, of whether the channel is available for transmission. If the channel is available for transmission, the available frame is transmitted over the channel in a subsequent slot of the slotted time base. If the channel is not available for transmission, owing to a frame (having a certain temporal length) being transmitted over the channel at a certain time, the slotted time base of the node is resynchronized as a function of the frame being transmitted. The resynchronization includes identifying, as a function of the certain temporal length, an interval of delay to evaluate again at a future time whether the channel is available for transmission.

    Abstract translation: 在通信网络中的信道上的数据帧的传输在时隙基础上进行。 一种方法包括由具有可用于传输的帧的网络的至少一个节点评估该信道是否可用于传输。 如果信道可用于传输,则可用帧在时隙时基的后续时隙中通过信道发送。 如果信道不可用于传输,则由于在特定时间通过信道发送帧(具有一定的时间长度),所述节点的时隙时基作为所发送帧的函数被重新同步。 重新同步包括根据特定时间长度识别延迟的间隔,以便在将来的时间再次评估信道是否可用于传输。

    Analog to digital conversion apparatus with a reduced number of ADCs
    10.
    发明授权
    Analog to digital conversion apparatus with a reduced number of ADCs 有权
    具有ADC数量减少的模数转换装置

    公开(公告)号:US08994565B2

    公开(公告)日:2015-03-31

    申请号:US14055874

    申请日:2013-10-16

    CPC classification number: H03M1/122

    Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.

    Abstract translation: 模数转换器包括用于接收模拟输入信号的多路复用器电路,并且响应于选择输入,模数转换器电路将所选择的模拟信号转换成数字信号,转换启动装置将转换开始信号发送到 触发事件的基础,转换启动装置响应于选择输入,定序器,用于控制模数转换器电路,以基于一个转换顺序指令执行一个序列转换;以及FIFO寄存器块,用于接收转换 序列指令,并且如果实际转换序列正在进行,并且能够对每个新的接收到的转换序列指令进行排队,并且在执行转换序列之后控制定序器执行新的序列转换指令。

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