Abstract:
A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.
Abstract:
Transmission of data frames over a channel in a communications network takes place on a slotted time base. A method comprises an evaluation, by at at least one node of the network having a frame available for transmission, of whether the channel is available for transmission. If the the channel is available for transmission, the available frame is transmitted over the channel in a subsequent slot of the slotted time base. If the channel is not available for transmission, owing to a frame (having a certain temporal length) being transmitted over the channel at a certain time, the slotted time base of the at least one node is resynchronized as a function of the frame being transmitted. The resynchronization includes identifying, as a function of the certain temporal length, an interval of delay to evaluate again in at a furture time whether the channel is available for transmission.
Abstract:
A method for control of an internal combustion engine includes generating, with a microelectromechanical system (MEMS) accelerometer, an acceleration signal representing vibrations of the internal combustion engine. An engine crank angle signal is generated based on the acceleration signal. The engine crank angle signal is compared with a target value. The internal combustion engine is adjusted based upon the comparing.
Abstract:
A GOP-independent dynamic bit-rate controller system includes a user interface to receive one or more input parameters, a bit-rate controller and an encoder. The bit-rate controller regulates a bit-rate of an output bit-stream. The bit-rate controller includes multiple bit-rate modules to determine a bit-estimate and a quantization parameter, and a control module to calculate a convergence period based on the received input parameters and a frame rate. The control module selects a bit rate module based on the convergence period and the encoder generates the output bit-stream using the quantization parameter determined by the bit rate module.
Abstract:
The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.
Abstract:
A system comprises a resource, such as an interconnection, for example, of the Network-on-Chip (NoC) type, having an overall bandwidth available for allocation to a set of initiators that compete for allocation of the overall bandwidth. The system includes a communication arbiter for allocating the overall bandwidth to the initiators according to respective values of bandwidth requested (RBW) by the initiators. A control device (50) is configured to detect the deviation between the value of bandwidth allocated to the initiators and the respective value of requested bandwidth and allocate the overall bandwidth to the initiators in a dynamic way minimizing the mean value of the deviation.
Abstract:
A method for control of an internal combustion engine includes generating, with a microelectromechanical system (MEMS) accelerometer, an acceleration signal representing vibrations of the internal combustion engine. An engine crank angle signal is generated based on the acceleration signal. The engine crank angle signal is compared with a target value. The internal combustion engine is adjusted based upon the comparing.
Abstract:
An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.
Abstract:
Transmission of data frames over a channel in a communications network takes place on a slotted time base. A method comprises an evaluation, by at least one node of the network having a frame available for transmission, of whether the channel is available for transmission. If the channel is available for transmission, the available frame is transmitted over the channel in a subsequent slot of the slotted time base. If the channel is not available for transmission, owing to a frame (having a certain temporal length) being transmitted over the channel at a certain time, the slotted time base of the node is resynchronized as a function of the frame being transmitted. The resynchronization includes identifying, as a function of the certain temporal length, an interval of delay to evaluate again at a future time whether the channel is available for transmission.
Abstract:
An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.