公开(公告)号：US06408379B1

公开(公告)日：2002-06-18

申请号：US09329718

申请日：1999-06-10

Applicant: Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

Inventor： Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

IPC: G06F738

CPC classification number: G06F9/3861 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/4991 ,  G06F9/30014

Abstract: An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

Abstract translation: 提供了一种用于在微处理器中执行浮点存储指令的装置和方法。 如果浮点存储指令的存储数据对应于微数，并且下溢异常被屏蔽，则可以执行陷阱例程以生成校正的存储数据并完成存储操作。 响应于检测到存储数据对应于微小数字并且下溢异常被屏蔽，可以在启动陷阱例程之前存储存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为访问存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为生成更正的存储数据，并使用存储数据，存储地址信息和操作码信息完成存储操作。

公开(公告)号：US06223198B1

公开(公告)日：2001-04-24

申请号：US09134171

申请日：1998-08-14

Applicant: Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

Inventor： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

IPC: G06F752

CPC classification number: G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.

公开(公告)号：US20060101242A1

公开(公告)日：2006-05-11

申请号：US10985291

申请日：2004-11-10

Applicant: Ming Siu ,  Stuart Oberman

Inventor： Ming Siu ,  Stuart Oberman

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3875

Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and comparison testing operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and format conversion operations.

Abstract translation: 多用途功能单元可配置为支持多种操作，包括乘法和比较测试操作，以及其他整数和/或浮点运算，布尔运算和格式转换操作。

公开(公告)号：US06269384B1

公开(公告)日：2001-07-31

申请号：US09049752

申请日：1998-03-27

Applicant: Stuart Oberman

Inventor： Stuart Oberman

IPC: G06F738

CPC classification number: G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur.

Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以基于每个操作数的最高有效位和控制信号来计算乘法器和被乘数操作数的有效符号。 然后根据布斯算法，有效符号可用于创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。

公开(公告)号：US06029244A

公开(公告)日：2000-02-22

申请号：US948679

申请日：1997-10-10

Applicant: Stuart Oberman ,  Norbert Juffa

Inventor： Stuart Oberman ,  Norbert Juffa

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F17/16 ,  G06F9/305

CPC classification number: G06F17/16 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

公开(公告)号：US20060149803A1

公开(公告)日：2006-07-06

申请号：US10985674

申请日：2004-11-10

Applicant: Ming Siu ,  Stuart Oberman

Inventor： Ming Siu ,  Stuart Oberman

IPC: G06F9/44

CPC classification number: G06F9/30014 ,  G06F9/3885

Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations.

Abstract translation: 多用途功能单元可配置为支持多种操作，包括乘法加法和格式转换操作，以及其他整数和/或浮点算术运算，布尔运算和逻辑运算。

公开(公告)号：US20060101244A1

公开(公告)日：2006-05-11

申请号：US10986531

申请日：2004-11-10

Applicant: Ming Siu ,  Stuart Oberman

Inventor： Ming Siu ,  Stuart Oberman

IPC: G06F9/44

CPC classification number: G06F9/3885 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/3875

Abstract: A multipurpose functional unit is configurable to support a number of operations including floating-point and integer multiply-add, operations as well as other integer and/or floating-point arithmetic operations, Boolean operations, comparison testing operations, and format conversion operations.

Abstract translation: 多用途功能单元可配置为支持多种操作，包括浮点和整数乘法运算，以及其他整数和/或浮点运算，布尔运算，比较测试运算和格式转换运算。

公开(公告)号：US06557098B2

公开(公告)日：2003-04-29

申请号：US09478139

申请日：2000-01-05

Applicant: Stuart Oberman ,  Norbert Juffa

Inventor： Stuart Oberman ,  Norbert Juffa

IPC: G06F9305

CPC classification number: G06F17/16 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

Abstract translation: 提供执行单元，用于执行包括操作码字段，第一操作数字段和第二操作数字段的第一指令。 执行单元包括用于接收由第一操作数字段的值指定的第一操作数的第一输入寄存器和用于接收由第二操作数字段的值指定的第二操作数的第二输入寄存器。 执行单元还包括比较器单元，其被耦合以接收第一指令的操作码字段的值。 比较器单元还被耦合以分别从第一和第二输入寄存器接收第一和第二操作数值。 执行还包括接收多个输入的多路复用器。 这些输入包括第一常数值，第二常数值以及第一和第二操作数的值。 如果由比较器接收的解码的操作码值指示第一指令是比较值或极值函数，则比较器将一个或多个控制信号传送到多路复用器，以便作为第一个指令的结果来选择多路复用器的输出 指令。 如果第一指令是多个极值指令之一，则由比较器单元传送的一个或多个控制信号在第一操作数和第二操作数之间进行选择，以确定第一指令的结果。 如果第一指令是多个比较指令之一，则由比较器单元传送的一个或多个控制信号在第一和第二常数值之间进行选择，以确定第一指令的结果。 在另一个实施例中，提供了处理向量操作数的类似执行单元。

公开(公告)号：US6085213A

公开(公告)日：2000-07-04

申请号：US49789

申请日：1998-03-27

Applicant: Stuart Oberman ,  Ming Siu

Inventor： Stuart Oberman ,  Ming Siu

IPC: G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F7/53 ,  G06F17/16 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F2207/3828 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338

Abstract: A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated based upon each operand's most significant bit and a control signal. The effective signs may then be used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur.

Abstract translation: 公开了能够执行有符号和无符号标量和矢量乘法的乘法器。 乘法器配置为以标量或压缩向量形式接收带符号或无符号乘数和被乘数操作数。 可以基于每个操作数的最高有效位和控制信号来计算乘法器和被乘数操作数的有效符号。 然后根据布斯算法，有效符号可用于创建和选择多个部分乘积。 一旦创建并选择了部分产品，就可以对它们进行求和并输出结果。 结果可能是有符号或无符号的，可能表示向量或标量。 当执行向量乘法时，乘法器可以被配置为产生和选择部分乘积，以便有效地隔离每对向量分量的乘法过程。 乘法器还可以被配置为对矢量分量的乘积求和以形成向量点积。 最终产品可以分段输出，以便需要更少的总线。 可以通过添加舍入常数来对段进行舍入。 可以在两个路径中执行舍入和归一化，一个假设将发生溢出，另一个假设不会发生溢出。

公开(公告)号：US08106914B2

公开(公告)日：2012-01-31

申请号：US11952858

申请日：2007-12-07

Applicant: Stuart Oberman ,  Ming Y. Siu ,  David C. Tannenbaum

Inventor： Stuart Oberman ,  Ming Y. Siu ,  David C. Tannenbaum

IPC: G06T1/20 ,  G06T1/00 ,  G06T15/00 ,  G06F15/16 ,  G06F7/38

CPC classification number: G06F9/30014 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3893 ,  G06T1/20

Abstract: A functional unit is added to a graphics processor to provide direct support for double-precision arithmetic, in addition to the single-precision functional units used for rendering. The double-precision functional unit can execute a number of different operations, including fused multiply-add, on double-precision inputs using data paths and/or logic circuits that are at least double-precision width. The double-precision and single-precision functional units can be controlled by a shared instruction issue circuit, and the number of copies of the double-precision functional unit included in a core can be less than the number of copies of the single-precision functional units, thereby reducing the effect of adding support for double-precision on chip area.

Abstract translation: 除了用于渲染的单精度功能单元之外，功能单元被添加到图形处理器以提供对双精度算术的直接支持。 双精度功能单元可以使用至少双精度宽度的数据路径和/或逻辑电路在双精度输入上执行多种不同的操作，包括融合乘法运算。 双精度和单精度功能单元可以由共享指令发出电路控制，核心中包含的双精度功能单元的份数可以小于单精度功能的副本数 单位，从而降低了对双精度芯片面积的支持的影响。