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    Exposure method of semiconductor pattern
    2.
    发明申请
    Exposure method of semiconductor pattern 有权

    公开(公告)号：US20250102922A1

    公开(公告)日：2025-03-27

    申请号：US18382528

    申请日：2023-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

    IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

    Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

    ESD GUARD RING STRUCTURE AND FABRICATING METHOD OF THE SAME
    5.
    发明申请
    ESD GUARD RING STRUCTURE AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20250098333A1

    公开(公告)日：2025-03-20

    申请号：US18380647

    申请日：2023-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun

    IPC: H01L27/02

    Abstract: An ESD guard ring structure includes numerous first fin structures, numerous second fin structures, numerous first polysilicon conductive lines, numerous second polysilicon conductive lines, numerous third polysilicon conductive lines and numerous single diffusion breaks. Each of the first fin structures includes at least one single diffusion break therein. Each of the single diffusion breaks overlaps one of the third polysilicon conductive lines.

    Manufacturing method of semiconductor device
    6.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US12255245B2

    公开(公告)日：2025-03-18

    申请号：US18590985

    申请日：2024-02-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Yu Yang

    IPC: H01L29/423 ,  H01L27/092 ,  H01L29/786

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first transistor is formed on a substrate. The first transistor includes a first semiconductor channel structure and two first source/drain structures. The first semiconductor channel structure includes first horizontal portions and a first vertical portion. The first horizontal portions are stacked in a vertical direction and separated from one another. Each of the first horizontal portions is elongated in a horizontal direction. The first vertical portion is elongated in the vertical direction and connected with the first horizontal portions. The two first source/drain structures are disposed at two opposite sides of each of the first horizontal portions in the horizontal direction respectively. The two first source/drain structures are connected with the first horizontal portions. A top surface of the first vertical portion in and a top surface of one of the first horizontal portions are coplanar.

    STRUCTURE WITH CAPACITOR AND FIN TRANSISTOR AND FABRICATING METHOD OF THE SAME
    7.
    发明申请
    STRUCTURE WITH CAPACITOR AND FIN TRANSISTOR AND FABRICATING METHOD OF THE SAME 有权

    公开(公告)号：US20250089349A1

    公开(公告)日：2025-03-13

    申请号：US18381639

    申请日：2023-10-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hao Lin

    IPC: H01L27/06 ,  H01L21/265 ,  H01L21/762 ,  H01L29/78

    Abstract: A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250089281A1

    公开(公告)日：2025-03-13

    申请号：US18487110

    申请日：2023-10-15

    Applicant: United Microelectronics Corp.

    Inventor： Wen-Kai Lin ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

    IPC: H01L29/872 ,  H01L29/40 ,  H01L29/47 ,  H01L29/66

    Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    9.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权

    公开(公告)号：US20250072042A1

    公开(公告)日：2025-02-27

    申请号：US18376450

    申请日：2023-10-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tzu-Hsin Chen ,  Mei-Ling Chao ,  Tien-Hao Tang ,  Kuan-cheng Su

    IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08

    Abstract: An electrostatic discharge protection device includes a substrate, a well region of a first conductivity type in the substrate, a drain field region and a source field region of a second conductivity type in the well region, a gate structure on the well region and between the drain field region and the source field region, a drain contact region and a source contact region of the second conductivity type respectively in the drain field region and the source field region, a first isolation region in the drain field region and between the drain contact region and the gate structure, and a drain doped region of the first conductivity in the drain field region and between a portion of a bottom surface of the drain contact region and the drain field region.

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