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1.发明授权公开(公告)号：US08316191B2
公开(公告)日：2012-11-20
申请号：US12207476
申请日：2008-09-09
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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公开(公告)号：US20090290387A1
公开(公告)日：2009-11-26
申请号：US12246620
申请日：2008-10-07
申请人： William R. Wheeler , Wei-Liang Lin
发明人： William R. Wheeler , Wei-Liang Lin
IPC分类号： H02M3/335
CPC分类号： H02M3/33507 , H02M2001/007
摘要： A switching power supply with the increased efficiency at light load has a switching power circuit, a power monitoring circuit and a light load power supplying circuit. The switching power circuit converts an AC power to a stable DC power and sends the DC power to a load according to voltage variation of the load. When the power monitoring circuit detects the AC power and determines that the load is in a light state, the power monitoring circuit controls the light load power supplying circuit to output a small-power DC to the load. As the DC power provided by the light load power supplying circuit is small, the switching loss ratio is lower in its light load state. Therefore, the operating efficiency at the light load state is higher.
摘要翻译： 具有提高轻负载效率的开关电源具有开关电源电路，功率监视电路和轻负载供电电路。 开关电源电路将交流电转换成稳定的直流电力，并根据负载的电压变化将直流电力发送到负载。 当电源监视电路检测到交流电源并确定负载处于亮状态时，电力监控电路控制轻负载供电电路向负载输出小功率DC。 由于轻负载供电电路提供的直流电力小，其轻负载状态下的开关损耗率较低。 因此，轻负载状态下的工作效率较高。
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3.发明授权Memory controller for processor having multiple multithreaded programmable units 有权具有多个多线程可编程单元的处理器的存储器控制器公开(公告)号：US07424579B2
公开(公告)日：2008-09-09
申请号：US11232566
申请日：2005-09-21
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 所述处理器还包括存储器控制系统，所述存储器控制系统具有第一存储器控制器，所述第一存储器控制器基于所述存储器引用是针对偶数存储体还是存储器的奇数存储器排序存储器引用;以及第二存储器控制器， 内存引用是读取引用或写入引用。
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公开(公告)号：US07197724B2
公开(公告)日：2007-03-27
申请号：US10054179
申请日：2002-01-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Modeling a logic design includes displaying a menu comprised of different types of functional block diagrams, receiving an input selecting one of the different types of functional block diagrams, retrieving a selected functional block diagram, and creating a graphical representation of a logic design using the selected functional block diagram. The graphical representation is created by interconnecting the selected functional block diagram with one or more other functional block diagrams to generate a model of a logic design and defining the selected functional block diagram using simulation code if the functional block diagram is undefined when retrieved.
摘要翻译： 建模逻辑设计包括显示由不同类型的功能框图组成的菜单，接收选择不同类型的功能框图之一的输入，检索选定的功能框图，以及使用所选择的功能块图创建逻辑设计的图形表示 功能框图。 通过将所选择的功能框图与一个或多个其他功能框图互连来产生图形表示，以便如果在检索到功能框图未定义时，使用模拟代码来生成逻辑设计的模型并定义所选择的功能框图。
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公开(公告)号：US07100430B2
公开(公告)日：2006-09-05
申请号：US10867922
申请日：2004-06-14
CPC分类号： G01Q10/04 , G01B3/008 , G01B7/34 , G01Q10/02 , G01Q30/02 , G01Q70/06 , Y10S977/834 , Y10S977/849 , Y10S977/852 , Y10S977/867 , Y10S977/868 , Y10S977/872 , Y10S977/874
摘要： A dual stage scanning instrument includes a sensor for sensing a parameter of a sample and coarse and fine stages for causing relative motion between the sensor and the sample. The coarse stage has a resolution of about 1 micrometer and the fine stage has a resolution of 1 nanometer or better. The sensor is used to sense the parameter when both stages cause relative motion between the sensor assembly and the sample. The sensor may be used to sense height variations of the sample surface as well as thermal variations, electrostatic, magnetic, light reflectivity or light transmission parameters at the same time when height variation is sensed. By performing along scan at a coarser resolution and short scans a high resolution using the same probe tip or two probe tips at fixed relative positions, data obtained from the long and short scans can be correlated accurately.
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公开(公告)号：US06859913B2
公开(公告)日：2005-02-22
申请号：US10041753
申请日：2002-01-07
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A method includes sending a query from graphical user interface to a hardware configuration database. The query requests information located within a simulation model. The hardware configuration database including locations of hardware devices. The hardware devices represent functional processes. The method also includes searching the functional processes to locate the information and directly accessing the information in the simulation model from the graphical user interface without assistance from the hardware configuration database.
摘要翻译： 一种方法包括将查询从图形用户界面发送到硬件配置数据库。 查询请求位于模拟模型内的信息。 硬件配置数据库包括硬件设备的位置。 硬件设备代表功能过程。 该方法还包括搜索功能过程以定位信息，并且在没有硬件配置数据库的帮助下从图形用户界面直接访问模拟模型中的信息。
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7.发明授权公开(公告)号：US06823438B2
公开(公告)日：2004-11-23
申请号：US10746876
申请日：2003-12-23
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.
摘要翻译： 一种用于具有数字处理系统的存储器分配的装置和方法，包括第一存储体，硬件寄存器和配置为将硬件寄存器的内容写入第一存储体中的存储器地址的处理电路，并且将存储器地址 到硬件寄存器。 在一个实施例中，可以在第一存储体中保持包含存储器指针值的指针列表。 第一存储体可以包含相关联的数据缓冲器，并且第二存储体可以包含相应的数据缓冲器，使得可以从单个存储器指针值定位相关联的数据缓冲器和对应的数据缓冲器。
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公开(公告)号：US06708321B2
公开(公告)日：2004-03-16
申请号：US10038706
申请日：2002-01-04
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A method of generating a function within a logic design of a circuit, includes representing the function using an operator. The function has n operands, where n>1. The method also includes presenting the function within a schematic representation of the logic design. Other features may include displaying a dialog box and inputting data that corresponds to the function.
摘要翻译： 在电路的逻辑设计中产生功能的方法包括使用操作者来表示功能。 该函数具有n个操作数，其中n> 1。 该方法还包括在逻辑设计的示意图中呈现功能。 其他特征可以包括显示对话框并输入对应于该功能的数据。
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公开(公告)号：US06643836B2
公开(公告)日：2003-11-04
申请号：US09941923
申请日：2001-08-29
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Displaying information relating to a logic design includes generating a first display that relates to the logic design, the first display being associated with other information not included in the first display, retrieving the other information in response to a user input, and generating a second display that relates to the logic design based on the other information.
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公开(公告)号：US6052706A
公开(公告)日：2000-04-18
申请号：US977732
申请日：1997-11-25
IPC分类号： G06F7/52
CPC分类号： G06F7/5324 , G06F7/5338 , G06F7/535 , G06F2207/3884 , G06F2207/5352
摘要： In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process. The foregoing arrangement provides a flexible approach which can be adapted for particular bandwidth requirements and constraints which vary with each particular application and system in which such a process is performed.
摘要翻译： 根据本发明，提供了一种用于对数据流执行迭代处理的电路。 迭代过程包括对数据流的一部分进行操作以产生作为后级的输入的输出的流水线级。 流水线级中的至少一个包括用于在将输出传递到后级之前将来自流水线级的输出作为输入再循环到流水线级预定次数的装置。 预定次数表示包括多于一个时钟信号的断言的时钟周期。 通过这样的布置，根据特定带宽要求执行诸如乘法和除法的处理的电路比执行相同处理的其它电路中需要的硬件要少。 上述布置提供了一种灵活的方法，该方法可以针对特定的带宽要求和约束进行调整，每个特定的应用和系统在执行这种处理的每一个特定的应用和系统中
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