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    Liquid crystal display device and driving method thereof
    1.
    发明授权
    Liquid crystal display device and driving method thereof 有权
    液晶显示装置及其驱动方法

    公开(公告)号：US09087493B2

    公开(公告)日：2015-07-21

    申请号：US11945669

    申请日：2007-11-27

    申请人： Yong-Chae Jung ,  Min-Hwa Kim

    发明人： Yong-Chae Jung ,  Min-Hwa Kim

    IPC分类号： G09G3/36 ,  G09G3/32

    CPC分类号： G09G3/3688 ,  G09G3/3266 ,  G09G2320/0214

    摘要： A liquid crystal display device includes a liquid crystal panel, a gate driver, a data driver, and an initial driving control unit. The liquid crystal panel includes a plurality of liquid crystal cells. Each liquid crystal cell is defined by a gate line, a data line and a thin film transistor. The gate driver controls the thin film transistor connected to the gate line of each liquid crystal cell according to a gate control signal. The data driver outputs a pixel signal to the data line of the each liquid crystal cell according to a data control signal. The data driver includes a switch connected to the data line of the each liquid crystal cell. The initial driving control unit is structured to compare a clock count with a predetermined reference value and operable to alternately generate a first state signal and a second state signal based on the comparison. The unit applies the first state signal to the switch during a masking interval. The pixel signal is not output to the data line during the masking interval.

    摘要翻译： 液晶显示装置包括液晶面板，栅极驱动器，数据驱动器和初始驱动控制单元。 液晶面板包括多个液晶单元。 每个液晶单元由栅极线，数据线和薄膜晶体管限定。 栅极驱动器根据栅极控制信号控制连接到每个液晶单元的栅极线的薄膜晶体管。 数据驱动器根据数据控制信号将像素信号输出到每个液晶单元的数据线。 数据驱动器包括连接到每个液晶单元的数据线的开关。 初始驱动控制单元被构造为将时钟计数与预定参考值进行比较，并且可操作以基于该比较交替地产生第一状态信号和第二状态信号。 在屏蔽间隔期间，该单元将第一状态信号施加到开关。 在屏蔽间隔期间，像素信号不输出到数据线。

    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    4.
    发明申请
    VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直存储器件及其制造方法

    公开(公告)号：US20140070300A1

    公开(公告)日：2014-03-13

    申请号：US13724187

    申请日：2012-12-21

    申请人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

    发明人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

    摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

    摘要翻译： 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

    Vertical memory devices and methods of manufacturing the same
    7.
    发明授权
    Vertical memory devices and methods of manufacturing the same 有权
    垂直存储器件及其制造方法

    公开(公告)号：US08916922B2

    公开(公告)日：2014-12-23

    申请号：US13724187

    申请日：2012-12-21

    申请人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

    发明人： Kyung-Tae Jang ,  Myoung-Bum Lee ,  Ji-Youn Seo ,  Chang-Won Lee ,  Yong-Chae Jung ,  Woong-Hee Sohn

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

    摘要： A semiconductor device includes a substrate, a plurality of insulating layers vertically stacked on the substrate, a plurality of channels arranged in vertical openings formed through at least some of the plurality of insulating layers, and a plurality of portions alternatingly positioned with the plurality of insulating layers in the vertical direction. At least some of the portions are adjacent corresponding channels of the plurality of channels. Each of the portions includes a conductive barrier pattern formed on an inner wall of the portion, a filling layer pattern positioned in the portion on the conductive barrier pattern, and a gate electrode positioned in a remaining area of the portion not occupied by the conductive barrier or filling layer pattern.

    摘要翻译： 半导体器件包括衬底，垂直堆叠在衬底上的多个绝缘层，多个通道，布置在通过多个绝缘层中的至少一些形成的垂直开口中，以及多个部分交替地与多个绝缘体 层在垂直方向。 这些部分中的至少一些是相邻的多个通道的相应通道。 每个部分包括形成在该部分的内壁上的导电阻挡图案，位于导电阻挡图案上的部分中的填充层图案，以及位于未被导电屏障占据部分的剩余区域中的栅电极 或填充层图案。

    Semiconductor Memory Device and Method of Fabricating the Same
    8.
    发明申请
    Semiconductor Memory Device and Method of Fabricating the Same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20140220750A1

    公开(公告)日：2014-08-07

    申请号：US14171056

    申请日：2014-02-03

    申请人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    发明人： Woonghee Sohn ,  Kihyun Yun ,  Myoungbum Lee ,  Jeonggil Lee ,  Tai-Soo Lim ,  Yong Chae Jung

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

    摘要翻译： 提供半导体器件及其制造方法。 该方法可以包括形成包括绝缘层和交替层叠在基板上的电极层的电极结构，形成穿透电极结构的通道孔，在通道孔的侧壁上形成数据存储层，以及在通孔上形成半导体图案 数据存储层的侧壁将被电连接到基板。 电极层可以是金属硅化物层，并且可以使用相同的沉积系统以原位方式形成绝缘层和电极层。