公开(公告)号：US20230163691A1

公开(公告)日：2023-05-25

申请号：US17535341

申请日：2021-11-24

Applicant: ABB Schweiz AG

Inventor： Yuxiang Shi ,  Jing Xu ,  Utkarsh Raheja

IPC: H02M3/335 ,  H02M1/00

CPC classification number: H02M3/335 ,  H02M1/0003

Abstract: A device for load line regulation of a sigma convert is provided. The device comprises a sigma converter comprising an inductor inductor capacitor (LLC) circuit and a buck converter. The device also comprises control circuitry for the sigma converter. The control circuitry is configured to receive a plurality of electrical measurements associated with the sigma converter; determine, based on the plurality of electrical measurements, an adjusted electrical characteristic for load line regulation of the sigma converter; and provide, based on the adjusted electrical characteristic, gating signals to the buck converter to perform the load line regulation of the sigma converter.

公开(公告)号：US11955900B2

公开(公告)日：2024-04-09

申请号：US17363802

申请日：2021-06-30

Applicant: ABB Schweiz AG

Inventor： Utkarsh Raheja ,  Eddy Aeloiza ,  Pietro Cairoli

IPC: H02M5/458 ,  H02H7/08 ,  H02M1/36 ,  H02P1/26 ,  H03K17/13

CPC classification number: H02M5/458 ,  H02H7/0833 ,  H02M1/36 ,  H02P1/26 ,  H03K17/133

Abstract: A bi-directional switch for an inductive machine is described. The bi-directional switch may include a first power semiconductor transistor with a first source, a first drain, and a first gate. The bi-directional switch may further include a second power semiconductor transistor with a second source, a second drain, and a second gate. The bi-directional switch may include the second source connected to the first source. The bi-directional switch may include a soft-starter device including a control circuit configurable to provide a first control signal to the first power semiconductor transistor and a second control signal to the second power semiconductor transistor.

公开(公告)号：US20230179119A1

公开(公告)日：2023-06-08

申请号：US17541784

申请日：2021-12-03

Applicant: ABB Schweiz AG

Inventor： Eddy C. Aeloiza ,  Sayan Acharya ,  Utkarsh Raheja

IPC: H02M7/5387 ,  H02P27/06

CPC classification number: H02M7/53875 ,  H02P27/06

Abstract: An insulated gate field effect transistor (IGFET) based converter circuit is described that includes a direct current input comprising a high voltage input and a low voltage input, an IGFET gate input, and an equivalent phase leg comprising a plurality of parallel-connected cells. The parallel-connected cells each include: a first wide bandgap IGFET having a first drain electrode connected to the high voltage input, a first gate electrode connected to a first gate control input, and a first source electrode; a second wide bandgap IGFET having a second drain electrode connected to the first source electrode, a second gate electrode connected to a second gate control input, and a second source electrode connected to the low voltage input; and a step-inducing inductor coupled to: the first source electrode of the first wide bandgap IGFET, and an output node. The step-inducing inductor is connected to the output node.

公开(公告)号：US20240071704A1

公开(公告)日：2024-02-29

申请号：US17894740

申请日：2022-08-24

Applicant: ABB Schweiz AG

Inventor： Rostan Rodrigues ,  Pietro Cairoli ,  Utkarsh Raheja

IPC: H01H71/12 ,  H01L29/747 ,  H02H1/00 ,  H02H3/093

CPC classification number: H01H71/123 ,  H01L29/747 ,  H02H1/0007 ,  H02H3/093

Abstract: In one aspect, a solid-state circuit breaker (SSCB) is provided. The SSCB is configured to generate a first output representative of a current through a current path of the SSCB. An analog fault detection circuit is coupled with first output and is configured to assert a second output in response to the current exceeding a trip current level. At least one analog-to-digital converter (ADC) is configured to generate samples of the first output, where the at least one ADC has a di/dt detection bandwidth that is less than a di/dt detection bandwidth of the analog fault detection circuit. The SSCB is further configured to disable the current path through the SSCB in response to determining, asynchronously, that either the second output is being asserted by the analog fault detection circuit or the samples indicate that the current through the current path exceeds the trip current level.

公开(公告)号：US11196415B2

公开(公告)日：2021-12-07

申请号：US17029875

申请日：2020-09-23

Applicant: ABB SCHWEIZ AG

Inventor： Pietro Cairoli ,  Utkarsh Raheja ,  Thiago-Batista Soeiro ,  Lukas Hofstetter ,  Matthias Bator

IPC: H03K17/687 ,  H03K17/567

Abstract: A system for providing bi-directional power flow and power conditioning for high-voltage applications. The system including a normally-off four-quadrant power electronic switch having two gates and two normally-on junction field-effect transistor. The normally-off four-quadrant power electronic switch and the two normally-on junction field-effect transistors are coupled to one another in a bi-cascode configuration.

公开(公告)号：US12119817B2

公开(公告)日：2024-10-15

申请号：US17549520

申请日：2021-12-13

Applicant: ABB Schweiz AG

Inventor： Xiaoqing Song ,  Utkarsh Raheja ,  Pietro Cairoli ,  Sayan Acharya

IPC: H03K17/687 ,  H02H3/087 ,  H02H7/22

CPC classification number: H03K17/6874 ,  H02H3/087 ,  H02H7/22

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

公开(公告)号：US11831251B2

公开(公告)日：2023-11-28

申请号：US17541784

申请日：2021-12-03

Applicant: ABB Schweiz AG

Inventor： Eddy C. Aeloiza ,  Sayan Acharya ,  Utkarsh Raheja

IPC: H02M7/5387 ,  H02P27/06

CPC classification number: H02M7/53875 ,  H02P27/06

Abstract: An insulated gate field effect transistor (IGFET) based converter circuit is described that includes a direct current input comprising a high voltage input and a low voltage input, an IGFET gate input, and an equivalent phase leg comprising a plurality of parallel-connected cells. The parallel-connected cells each include: a first wide bandgap IGFET having a first drain electrode connected to the high voltage input, a first gate electrode connected to a first gate control input, and a first source electrode; a second wide bandgap IGFET having a second drain electrode connected to the first source electrode, a second gate electrode connected to a second gate control input, and a second source electrode connected to the low voltage input; and a step-inducing inductor coupled to: the first source electrode of the first wide bandgap IGFET, and an output node. The step-inducing inductor is connected to the output node.

公开(公告)号：US12148590B2

公开(公告)日：2024-11-19

申请号：US17894740

申请日：2022-08-24

Applicant: ABB Schweiz AG

Inventor： Rostan Rodrigues ,  Pietro Cairoli ,  Utkarsh Raheja

IPC: H01H71/12 ,  H01L29/747 ,  H02H1/00 ,  H02H3/093

Abstract: Solid-state circuit breakers and method of operating same are provided. A solid-state circuit breaker (SSCB) is configured to generate a first output representative of a current through a current path of the SSCB. An analog fault detection circuit is coupled with first output and is configured to assert a second output in response to the current exceeding a trip current level. At least one analog-to-digital converter (ADC) is configured to generate samples of the first output, where the at least one ADC has a di/dt detection bandwidth that is less than a di/dt detection bandwidth of the analog fault detection circuit. The SSCB is further configured to disable the current path through the SSCB in response to determining, asynchronously, that either the second output is being asserted by the analog fault detection circuit or the samples indicate that the current through the current path exceeds the trip current level.

公开(公告)号：US12074209B2

公开(公告)日：2024-08-27

申请号：US17468831

申请日：2021-09-08

Applicant: ABB Schweiz AG

Inventor： Xiaoqing Song ,  Utkarsh Raheja ,  Pietro Cairoli ,  Jing Xu

IPC: H02M1/32 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H02H3/08 ,  H03K17/0812

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/778 ,  H02H3/08 ,  H02M1/32 ,  H03K17/08122 ,  H03K2217/0027

Abstract: An overcurrent fault detector using a High Electron Mobility Transistor (HEMT) operated by a gate driver is disclosed. The overcurrent fault detector includes a band-pass filter and a control circuit. The band-pass filter is configured to receive gate-to-source voltage (VGS) signals of the HEMT and filter the VGS signals to generate a band-limited version of the VGS signals. The control circuit is configured to measure a value of the band-limited version of the VGS signals, determine if the value is greater than a threshold value, and generate a fault signal that disables the gate driver and terminates an overcurrent fault condition in response to determining that the value is greater than the threshold value.

公开(公告)号：US20230188134A1

公开(公告)日：2023-06-15

申请号：US17549520

申请日：2021-12-13

Applicant: ABB Schweiz AG

Inventor： Xiaoqing Song ,  Utkarsh Raheja ,  Pietro Cairoli ,  Sayan Acharya

IPC: H03K17/687 ,  H02H7/22 ,  H02H3/087

CPC classification number: H03K17/6874 ,  H02H7/22 ,  H02H3/087

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.