公开(公告)号：US20200089301A1

公开(公告)日：2020-03-19

申请号：US16133390

申请日：2018-09-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Alexander J. Branover

IPC: G06F1/32 ,  G06F9/54 ,  G06F9/4401

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

公开(公告)号：US20210191493A1

公开(公告)日：2021-06-24

申请号：US17193222

申请日：2021-03-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Alexander J. Branover

IPC: G06F1/3206 ,  G06F9/4401 ,  G06F9/54 ,  G06F1/3234

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

公开(公告)号：US12061510B2

公开(公告)日：2024-08-13

申请号：US17193222

申请日：2021-03-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Alexander J. Branover

IPC: G06F1/3206 ,  G06F1/3234 ,  G06F9/4401 ,  G06F9/54

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F9/4401 ,  G06F9/542

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

公开(公告)号：US20210191737A1

公开(公告)日：2021-06-24

申请号：US16718656

申请日：2019-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F9/4401 ,  G06F12/0804 ,  G06F1/3234 ,  G06F1/3287

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US12260225B2

公开(公告)日：2025-03-25

申请号：US17943265

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F9/4401 ,  G06F12/0804

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US11449346B2

公开(公告)日：2022-09-20

申请号：US16718656

申请日：2019-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F12/0804 ,  G06F9/4401

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US10955892B2

公开(公告)日：2021-03-23

申请号：US16133390

申请日：2018-09-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Alexander J. Branover

IPC: G06F1/3206 ,  G06F9/4401 ,  G06F9/54 ,  G06F1/3234

Abstract: The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.