公开(公告)号：US12117945B2

公开(公告)日：2024-10-15

申请号：US17849117

申请日：2022-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1621 ,  G06F13/1642

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US20180019006A1

公开(公告)日：2018-01-18

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G11C11/408

CPC classification number: G11C7/1063 ,  G06F12/1018 ,  G06F2212/1041 ,  G11C7/10 ,  G11C7/1072 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US20230418772A1

公开(公告)日：2023-12-28

申请号：US17849117

申请日：2022-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F13/1642 ,  G06F13/1621

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

公开(公告)号：US20210191737A1

公开(公告)日：2021-06-24

申请号：US16718656

申请日：2019-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F9/4401 ,  G06F12/0804 ,  G06F1/3234 ,  G06F1/3287

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US10684969B2

公开(公告)日：2020-06-16

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US12073114B2

公开(公告)日：2024-08-27

申请号：US17491058

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  Eric M. Scott

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0679

Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.

公开(公告)号：US20230102680A1

公开(公告)日：2023-03-30

申请号：US17491058

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  Eric M. Scott

IPC: G06F3/06

Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.

公开(公告)号：US20180018291A1

公开(公告)日：2018-01-18

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US12260225B2

公开(公告)日：2025-03-25

申请号：US17943265

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jyoti Raheja ,  Hideki Kanayama ,  Guhan Krishnan ,  Ruihua Peng

IPC: G06F1/3234 ,  G06F1/3287 ,  G06F9/4401 ,  G06F12/0804

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.

公开(公告)号：US20250061071A1

公开(公告)日：2025-02-20

申请号：US18909595

申请日：2024-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Hideki Kanayama ,  YuBin Yao

IPC: G06F13/16

Abstract: A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.