公开(公告)号：US20250070031A1

公开(公告)日：2025-02-27

申请号：US18944757

申请日：2024-11-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H LOH ,  Raja SWAMINATHAN ,  Rahul AGARWAL ,  Brett P. WILKERSON

IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

公开(公告)号：US20240330196A1

公开(公告)日：2024-10-03

申请号：US18388602

申请日：2023-11-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Samuel NAFFZIGER ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC: G06F12/0897 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20210098419A1

公开(公告)日：2021-04-01

申请号：US16585480

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC: H01L23/00 ,  H01L25/065 ,  G06F8/41

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.