公开(公告)号：US20190066352A1

公开(公告)日：2019-02-28

申请号：US15687108

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. KAZAKOV ,  Skyler J. SALEH ,  Ruijin WU ,  Sagar Shankar BHANDARE

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/80 ,  G06T9/00

Abstract: A pipeline is configured to access a memory that stores a texture block and metadata that encodes compression parameters of the texture block and a residency status of the texture block. A processor requests access to the metadata in conjunction with requesting data in the texture block to perform a shading operation. The pipeline selectively returns the data in the texture block to the processor depending on whether the metadata indicates that the texture block is resident in the memory. A cache can also be included to store a copy of the metadata that encodes the compression parameters of the texture block. The residency status and the metadata stored in the cache can be modified in response to requests to access the metadata stored in the cache.

公开(公告)号：US20230305981A1

公开(公告)日：2023-09-28

申请号：US18204604

申请日：2023-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU

IPC: G06F13/40 ,  G06T1/20 ,  G06F12/0815

CPC classification number: G06F13/4027 ,  G06T1/20 ,  G06F12/0815 ,  G06F2212/1032

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20210097013A1

公开(公告)日：2021-04-01

申请号：US16585452

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU

IPC: G06F13/40 ,  G06F12/0815 ,  G06T1/20

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via an active bridge chiplet. The active bridge chiplet is an active silicon die that bridges GPU chiplets and allows partitioning of systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20240330196A1

公开(公告)日：2024-10-03

申请号：US18388602

申请日：2023-11-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Samuel NAFFZIGER ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC: G06F12/0897 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F12/0897 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1024

Abstract: A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

公开(公告)号：US20210158599A1

公开(公告)日：2021-05-27

申请号：US16698624

申请日：2019-11-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/54

Abstract: An apparatus includes a command buffer configured to temporarily store commands. The apparatus also includes processing units disposed at a substrate. The processing units are configured to access a plurality of copies of a command from the command buffer. The processing units include first processing units (such as fixed function hardware blocks) to perform geometry operations indicated by the command on a set of primitives. The geometry operations are performed concurrently by the first processing units. The processing units also include second processing units (such as shaders) to process mutually exclusive sets of pixels generated by rasterizing the set of primitives. The apparatus also includes a cache to temporarily store the pixels after shading by the shaders. The processing units stop or interrupt processing commands in response to detecting a synchronization point and resume processing the commands in response to all the processing units completing commands before synchronization point.

公开(公告)号：US20210098419A1

公开(公告)日：2021-04-01

申请号：US16585480

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Skyler J. SALEH ,  Ruijin WU ,  Milind S. BHAGAVAT ,  Rahul AGARWAL

IPC: H01L23/00 ,  H01L25/065 ,  G06F8/41

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In some embodiments, a method of manufacture includes a face-to-face process in which a first GPU chiplet and a second GPU chiplet are bonded to a temporary carrier wafer. A face surface of an active bridge chiplet is bonded to a face surface of the first and second GPU chiplets before mounting the GPU chiplets to a carrier substrate. In other embodiments, a method of manufacture includes a face-to-back process in which a face surface of an active bridge chiplet is bonded to a back surface of the first and second GPU chiplets.