公开(公告)号：US11947380B2

公开(公告)日：2024-04-02

申请号：US17890520

申请日：2022-08-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar Sajja ,  Sreekanth Godey ,  Anirudh R. Acharya

IPC: G06F1/08 ,  G06F1/12 ,  G06F9/50 ,  G06F11/34

CPC classification number: G06F1/08 ,  G06F1/12 ,  G06F9/505 ,  G06F11/3409

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

公开(公告)号：US11861781B2

公开(公告)日：2024-01-02

申请号：US17134744

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sreekanth Godey ,  Ashkan Hosseinzadeh Namin ,  Seunghun Jin ,  Teik-Chung Tan

IPC: G06F1/3228 ,  G06T15/00 ,  G06F1/3212 ,  G06F9/50 ,  G06F1/3215 ,  G06F9/30

CPC classification number: G06T15/005 ,  G06F1/3212 ,  G06F1/3215 ,  G06F1/3228 ,  G06F9/30098 ,  G06F9/5011

Abstract: The graphics processing unit (GPU) of a processing system transitions to a low-power state between frame rendering operations according to an inter-frame power off process, where GPU state information is stored on retention hardware. The retention hardware can include retention random access memory (RAM) or retention flip-flops. The retention hardware is operable in an active mode and a retention mode, where read/write operations are enabled at the retention hardware in the active mode and disabled in the retention mode, but data stored on the retention hardware is still retained in the retention mode. The retention hardware is placed in the retention state between frame rendering operations. The GPU transitions from its low-power state to its active state upon receiving an indication that a new frame is ready to be rendered and is restored using the GPU state information stored at the retention hardware.

公开(公告)号：US11442495B2

公开(公告)日：2022-09-13

申请号：US17032701

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ranjith Kumar Sajja ,  Sreekanth Godey ,  Anirudh R. Acharya

IPC: G06F1/08 ,  G06F11/34 ,  G06F9/50 ,  G06F1/12

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.