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公开(公告)号：US20240273767A1
公开(公告)日：2024-08-15
申请号：US18434185
申请日：2024-02-06
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Saurabh SHARMA , Laurent LEFEBVRE , Sagar Shankar BHANDARE , Ruijin WU
CPC classification number: G06T9/00 , G06T1/60 , G06T2200/04
Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
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公开(公告)号：US20220092826A1
公开(公告)日：2022-03-24
申请号：US17030048
申请日：2020-09-23
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Saurabh SHARMA , Laurent LEFEBVRE , Sagar Shankar BHANDARE , Ruijin WU
Abstract: Sampling circuitry independently accesses channels of texture data that represent a set of pixels. One or more processing units separately compress the channels of the texture data and store compressed data representative of the channels of the texture data for the set of pixels. The channels can include a red channel, a blue channel, and a green channel that represent color values of the set of pixels and an alpha channel that represents degrees of transparency of the set of pixels. Storing the compressed data can include writing the compress data to portions of a cache. The processing units can identify a subset of the set of pixels that share a value of a first channel of the plurality of channels and represent the value of the first channel over the subset of the set of pixels using information representing the value, the first channel, and boundaries of the subset.
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公开(公告)号：US20210398242A1
公开(公告)日：2021-12-23
申请号：US17128388
申请日：2020-12-21
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
IPC: G06T1/20 , G06T1/60 , G06F12/0806 , G06F12/0888
Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.
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公开(公告)号：US20180276790A1
公开(公告)日：2018-09-27
申请号：US15843968
申请日：2017-12-15
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Michael MANTOR , Laurent LEFEBVRE , Mika TUOMI , Kiia KALLIO
Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.
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Patent Agency Ranking
公开(公告)号：US20220222770A1
公开(公告)日：2022-07-14
申请号：US17708500
申请日：2022-03-30
Applicant: ATI Technologies ULC
Inventor： Stephen L. MOREIN , Laurent LEFEBVRE , Andrew E. GRUBER , Andi SKENDE
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20230289916A1
公开(公告)日：2023-09-14
申请号：US18199452
申请日：2023-05-19
Applicant: ATI Technologies, ULC
Inventor： Laurent LEFEBVRE , Andrew GRUBER , Stephen MOREIN
CPC classification number: G06T1/20 , G06F9/3851 , G06T15/005 , G06T15/04 , G06T1/60 , G09G5/001 , G09G5/363
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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公开(公告)号：US20190279333A1
公开(公告)日：2019-09-12
申请号：US16424145
申请日：2019-05-28
Applicant: ATI Technologies ULC
Inventor： Laurent LEFEBVRE , Andrew Gruber , Stephen Morein
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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公开(公告)号：US20210233205A1
公开(公告)日：2021-07-29
申请号：US17230129
申请日：2021-04-14
Applicant: ATI Technologies ULC
Inventor： Stephen L. MOREIN , Laurent LEFEBVRE , Andrew E. GRUBER , Andi SKENDE
Abstract: A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20220261947A1
公开(公告)日：2022-08-18
申请号：US17661824
申请日：2022-05-03
Applicant: ATI Technologies ULC
Inventor： Laurent LEFEBVRE , Andrew GRUBER , Stephen MOREIN
Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.
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