中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.016 seconds)

    Debugging a computing device
    2.
    发明授权
    Debugging a computing device 有权

    公开(公告)号：US10078568B1

    公开(公告)日：2018-09-18

    申请号：US14954780

    申请日：2015-11-30

    Applicant: AMAZON TECHNOLOGIES, INC.

    Inventor： Gil Stoler ,  Yaniv Shapira

    IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22

    CPC classification number: G06F11/263 ,  G06F11/273

    Abstract: A system includes a host debugger to carry out a debugging flow on a computing device and a debug controller to couple the host debugger to the computing device. The debug controller receives a bit stream from the host debugger, converts the incoming bit stream into a command according to a protocol, determines whether the command is a first-stage read command or a second-stage read command, and issues the first-stage read command to a data path of the computing device. If the command is a second-stage read command, the debug controller causes a reservation register of the debug controller to provide a data value or status indication to the host debugger through the interface. The reservation register contains read data returned by the first-stage read command and, in response to the second-stage read command, provides a status indication when the first-stage read command has not yet returned read data.

    Traffic separation in a multi-chip system
    4.
    发明授权
    Traffic separation in a multi-chip system 有权

    公开(公告)号：US11836103B1

    公开(公告)日：2023-12-05

    申请号：US17455138

    申请日：2021-11-16

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Roi Ben Haim ,  Erez Izenberg ,  Adi Habusha ,  Yaniv Shapira

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4027 ,  G06F13/4221 ,  G06F2213/0026

    Abstract: Systems and methods are provided to differentiate different types of traffic going through the same physical channel such that the traffic flow for different traffic types does not impact each other. The physical channel can be configured to support a plurality of virtual channels. Each transaction that needs to be communicated through the physical channel can be classified into a certain traffic type, and each traffic type can be assigned to a virtual channel. Each transaction can be communicated on a respective virtual channel based on the corresponding traffic type. If the traffic flow through a first virtual channel for a transaction slows down, the traffic flow through a second virtual channel for another transaction can continue without getting impacted by the slow down on the first virtual channel.

    FLEXIBLE REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) COMPUTATION DEVICE
    5.
    发明申请
    FLEXIBLE REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) COMPUTATION DEVICE 审中-公开

    公开(公告)号：US20190129796A1

    公开(公告)日：2019-05-02

    申请号：US16160782

    申请日：2018-10-15

    Applicant: Amazon Technologies, Inc.

    Inventor： Ron Diamant ,  Nafea Bshara ,  Yaniv Shapira ,  Guy Nakibly

    IPC: G06F11/10 ,  G06F11/20

    Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.

    Non-coherent and coherent connections in a multi-chip system
    7.
    发明授权
    Non-coherent and coherent connections in a multi-chip system 有权

    公开(公告)号：US11880327B1

    公开(公告)日：2024-01-23

    申请号：US17643132

    申请日：2021-12-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Guy Nakibly ,  Barak Wasserstrom ,  Yaniv Shapira ,  Erez Izenberg ,  Adi Habusha

    IPC: G06F13/40

    CPC classification number: G06F13/4027

    Abstract: A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

    Dynamic processor core frequency adjustment
    8.
    发明授权
    Dynamic processor core frequency adjustment 有权

    公开(公告)号：US11106267B2

    公开(公告)日：2021-08-31

    申请号：US16698525

    申请日：2019-11-27

    Applicant: Amazon Technologies, Inc.

    Inventor： Larisa Goffman-Vinopal ,  Udi Sherel ,  Anat Arbely ,  Yaniv Shapira

    IPC: G06F1/00 ,  G06F11/30 ,  G06F1/324 ,  G06F1/08

    Abstract: A method for managing clock frequency in a multi-core integrated circuit includes determining a minimum allowable operating clock frequency and a maximum allowable operating clock frequency for an integrated circuit having a plurality of processor cores. A plurality of clock sources is configured to provide a corresponding plurality of clock frequencies between the minimum allowable operating clock frequency and the maximum allowable operating clock frequency. A total number of active processor cores is determined. If it is determined that all of the plurality the processor cores are active, all active processor cores are operated at the minimum allowable operating clock frequency. If it is determined that the total number of active processor cores is lower than a threshold number, the clock frequency of one or more active processor cores is increased based on available electrical current budget.

    Uniform memory access architecture
    9.
    发明授权
    Uniform memory access architecture 有权

    公开(公告)号：US10346342B1

    公开(公告)日：2019-07-09

    申请号：US15451982

    申请日：2017-03-07

    Applicant: Amazon Technologies, Inc.

    Inventor： Mark Bradley Davis ,  Thomas A. Volpe ,  Nafea Bshara ,  Yaniv Shapira ,  Adi Habusha

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/40

    Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Patent Agency Ranking