公开(公告)号：US10014826B2

公开(公告)日：2018-07-03

申请号：US14965580

申请日：2015-12-10

Applicant: ANALOG DEVICES, INC.

Inventor： Peter J. Katzin ,  Haoyang Yu ,  Guogong Wang

IPC: H03F3/193 ,  H03F1/02

CPC classification number: H03F1/0205 ,  H03F1/0272 ,  H03F3/193 ,  H03F3/1935 ,  H03F2200/102 ,  H03F2200/129 ,  H03F2200/144 ,  H03F2200/153 ,  H03F2200/18 ,  H03F2200/451

Abstract: Provided herein are apparatus and methods for power enhancement of self-biased distributed amplifiers with gate bias networks. By sampling output power a gate bias network with a filter network can adjust gate bias so as to improve the P1 dB compression point and the Psat saturation power level of a self-biased distributed amplifier. Advantageously the filter network can be derived using passive components thereby making it an easy to implement and cost effective approach to improve linearity and output power.

公开(公告)号：US11424196B2

公开(公告)日：2022-08-23

申请号：US16282148

申请日：2019-02-21

Applicant: ANALOG DEVICES, INC.

Inventor： John C. Mahon ,  Peter J. Katzin ,  Song Lin

IPC: H01L23/66 ,  H01L23/48 ,  H03H7/38 ,  H01L23/00

Abstract: An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier.

公开(公告)号：US20170170787A1

公开(公告)日：2017-06-15

申请号：US14965580

申请日：2015-12-10

Applicant: ANALOG DEVICES, INC.

Inventor： Peter J. Katzin ,  Haoyang Yu ,  Guogong Wang

IPC: H03F1/02 ,  H03F3/193

CPC classification number: H03F1/0205 ,  H03F1/0272 ,  H03F3/193 ,  H03F3/1935 ,  H03F2200/102 ,  H03F2200/129 ,  H03F2200/144 ,  H03F2200/153 ,  H03F2200/18 ,  H03F2200/451

Abstract: Provided herein are apparatus and methods for power enhancement of self-biased distributed amplifiers with gate bias networks. By sampling output power a gate bias network with a filter network can adjust gate bias so as to improve the P1 dB compression point and the Psat saturation power level of a self-biased distributed amplifier. Advantageously the filter network can be derived using passive components thereby making it an easy to implement and cost effective approach to improve linearity and output power.