Abstract:
Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity. In response to determining that the other integrated circuit is authorized to execute the activity, the processor circuit sends, to the other integrated circuit over a configurable direct connection, an authorization signal authorizing the other integrated circuit to execute the activity.
Abstract:
Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.
Abstract:
An apparatus, system and method for determining whether a battery alarm of a UE is asserted, reducing a transmission duty cycle of the UE to zero for a first predetermined time period when the battery alarm is asserted, determining whether the battery alarm has been de-asserted after the first predetermined time period and when the battery alarm has not been de-asserted, increasing the transmission duty cycle to a first threshold level for a second predetermined time period, wherein the first threshold level is less than a full transmission duty cycle of the UE. When the battery alarm has been de-asserted, increasing the transmission duty cycle to a second threshold level for a third predetermined time period, wherein the second threshold level is less than the full transmission duty cycle of the UE, and wherein the second threshold level is greater than the first threshold level.