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公开(公告)号：US20230385066A1
公开(公告)日：2023-11-30
申请号：US17752060
申请日：2022-05-24
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Michael Brian SCHINZLER , Yasuo ISHII , Jatin BHARTIA , Sumanth CHENGAD RAGHU
CPC classification number: G06F9/3848 , G06F9/3844 , G06F9/3806 , G06F1/03
Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.
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公开(公告)号：US20210397455A1
公开(公告)日：2021-12-23
申请号：US16906259
申请日：2020-06-19
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Thibaut Elie LANOIS , Frederic Claude Marie PIRY
Abstract: A data processing apparatus is provided, which is able to provide predictions for hard to predict instructions. Prediction circuitry generates predictions relating to predictable instructions in a stream, where the prediction circuitry comprises storage circuitry to store, in respect of each of the predictable instructions, a reference to a set of monitored instructions in the stream to be used for generating predictions for the predictable instructions. Processing circuitry receives the predictions from the prediction circuitry and executes the predictable instructions in the stream using the predictions. Programmable instruction correlation parameter storage circuitry stores a given correlation parameter between a given predictable instruction in the stream and a subset of the set of monitored instructions of the given predictable instruction, to assist the prediction circuitry in generating the predictions. If the programmable instruction correlation parameter storage circuitry is currently storing the given correlation parameter, the prediction circuitry generates a given prediction relating to the given predictable instruction based on the subset of the set of monitored instructions indicated in the programmable instruction correlation parameter storage circuitry. Otherwise the prediction circuitry generates the given prediction relating to the given predictable instruction based on the set of monitored instructions indicated in the storage circuitry.
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公开(公告)号：US20200065111A1
公开(公告)日：2020-02-27
申请号：US16106382
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Frederic Claude Marie PIRY , Albin Pierrick TONNERRE
Abstract: An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop prediction circuitry having a plurality of entries, where each entry is used to maintain branch outcome prediction information for a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. The branch prediction circuitry is arranged to analyse blocks of instructions and to produce a prediction result for each block that is dependent on branch outcome predictions made for any branch instructions appearing in the associated block. A prediction queue then stores the prediction results produced by the branch prediction circuitry in order to determine the instructions to be executed by the processing circuitry. When the block of instructions being analysed comprises a loop controlling branch instruction that has an active entry in the loop prediction circuitry, and a determined condition is detected in respect of the associated loop, the loop prediction circuitry is arranged to produce a prediction result that identifies multiple iterations of the loop. This can significantly boost prediction bandwidth for certain types of loop.
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公开(公告)号：US20250077233A1
公开(公告)日：2025-03-06
申请号：US18459602
申请日：2023-09-01
Applicant: ARM Limited
Inventor： Houdhaifa BOUZGUARROU , Michael Brian SCHINZLER
Abstract: A data processing apparatus is provided. It includes history storage circuitry that stores historic data of instructions and prediction circuitry that predicts a historic datum of a specific instruction based on subsets of the historic data of the instructions. The history storage circuitry overwrites the historic data of one of the instructions to form a corrupted instruction datum and at least one of the subsets of the historic data of the instructions includes the corrupted historic datum.
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公开(公告)号：US20250068427A1
公开(公告)日：2025-02-27
申请号：US18454158
申请日：2023-08-23
Applicant: Arm Limited
Abstract: An apparatus has pointer storage to store pointer values for a plurality of pointers and increment circuitry, responsive to a series of increment events, to differentially increment the pointer values of the pointers. Training circuitry comprises tracker circuitry to maintain a plurality of tracker entries and cache circuitry to maintain a plurality of cache entries. Each tracker entry identifies a control flow instruction, and each cache entry stores a resolved behaviour of an instance of a control flow instruction identified by a tracker entry. For a given control flow instruction identified in a given tracker entry, the training circuitry performs a training process to seek to determine, as an associated pointer for the given control flow instruction, a pointer from amongst the plurality of pointers whose pointer value increments in a manner that meets a correlation threshold with occurrence of instances of the given control flow instruction. Promotion circuitry, responsive to detection of the correlation threshold being met for the given control flow instruction, allocates a prediction entry within prediction circuitry to identify the given control flow instruction and the associated pointer, and a behaviour record is established within the prediction entry identifying the resolved behaviour for one or more instances of the given control flow instruction. The behaviour record is arranged such that each resolved behaviour is associated with the pointer value of the associated pointer at the time that resolved behaviour was observed. Responsive to a prediction trigger associated with a replay of a given instance of the given control flow instruction, the prediction circuitry determines, in dependence on a current pointer value of the associated pointer, a predicted behaviour of the given instance of the given control flow instruction from the behaviour record within the prediction entry.
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Patent Agency Ranking
公开(公告)号：US20230418609A1
公开(公告)日：2023-12-28
申请号：US17851266
申请日：2022-06-28
Applicant: Arm Limited
CPC classification number: G06F9/30058 , G06F9/3861
Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.
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公开(公告)号：US20210124586A1
公开(公告)日：2021-04-29
申请号：US16662438
申请日：2019-10-24
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Thibaut Elie LANOIS
IPC: G06F9/38 , G06F12/0875 , G06F9/30
Abstract: An apparatus and method are provided for handling incorrect branch direction predictions. The apparatus has processing circuitry for executing instructions, branch prediction circuitry for making branch direction predictions in respect of branch instructions, and fetch circuitry for fetching instructions from an instruction cache in dependence on the branch direction predictions and for forwarding the fetched instructions to the processing circuitry for execution. A cache location buffer stores cache location information for a given branch instruction for which accuracy of the branch direction predictions made by the branch prediction circuitry is below a determined threshold. The cache location information identifies where within the instruction cache one or more instructions are stored that will need to be executed in the event that a subsequent branch direction prediction made for the given branch instruction is incorrect. Control circuitry is responsive to such a subsequent branch direction prediction to obtain from the cache location buffer the cache location information and to provide the obtained cache location information to the fetch circuitry to enable the fetch circuitry to retrieve from the instruction cache the one or more instructions that are to be executed in the event that the processing circuitry does determine that the subsequent branch direction prediction was incorrect.
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公开(公告)号：US20250076962A1
公开(公告)日：2025-03-06
申请号：US18458339
申请日：2023-08-30
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Michael Brian SCHINZLER
IPC: G06F1/3287
Abstract: A data processing apparatus is provided. It includes first history storage circuitry that stores control flow information of control flow instructions. Second history storage circuitry stores a subset of the control flow information by considering a subset of the control flow instructions. Prediction circuitry produces a prediction for a specific one of the control flow instructions based on the subset of the control flow information and power control circuitry performs a determination of an extent to which the subset of the control flow information matches the control flow information and disables the prediction circuitry in dependence on a result of the determination.
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公开(公告)号：US20250068939A1
公开(公告)日：2025-02-27
申请号：US18455053
申请日：2023-08-24
Applicant: ARM Limited
IPC: G06N5/022
Abstract: Combiner circuitry generates a combined prediction associated with a given address based on combining respective sets of prediction information generated by two or more predictors. Predictor control circuitry determines, based on a lookup of a prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address. If this condition is satisfied, a lookup of the second predictor is suppressed and the prediction associated with the prediction input address is generated based on the prediction outcome predicted by the first predictor for the prediction input address.
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公开(公告)号：US20230195468A1
公开(公告)日：2023-06-22
申请号：US17557583
申请日：2021-12-21
Applicant: Arm Limited
Inventor： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Thibaut Elie LANOIS , Vincenzo CONSALES , Chang Joo LEE
CPC classification number: G06F9/3806 , G06F9/3844 , G06F9/3005
Abstract: An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence. When the confidence level for a particular multi-taken sequence satisfies a prediction confidence condition, the prediction confidence tracking circuitry allows the particular multi-taken sequence to be predicted by the prediction circuitry. The prediction circuitry causes the series of instructions and the target instruction for the particular multi-taken sequence to be identified in the fetch queue when the prediction circuitry predicts the particular multi-taken sequence and further predictions to be made starting from the target address for the particular multi-taken sequence.
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