公开(公告)号：US20180307430A1

公开(公告)日：2018-10-25

申请号：US15493609

申请日：2017-04-21

Applicant: ARM Limited

Inventor： Xabier ITURBE ,  Emre ÖZER ,  Balaji VENU ,  Antony John PENTON

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1076

Abstract: An apparatus and method are provided for increasing resilience to faults. The apparatus comprises processing circuitry for executing a plurality of code sequences including at least one critical code sequence, and configuration storage for storing mode control data for the processing circuitry. When the processing circuitry is executing a critical code sequence, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry, where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry. By increasing the resilience to faults, this reduces the chance that any such fault will manifest itself as an error in the processing operations being performed by the apparatus.

公开(公告)号：US20190121689A1

公开(公告)日：2019-04-25

申请号：US16225523

申请日：2018-12-19

Applicant: ARM Limited

Inventor： Reiley JEYAPAUL ,  Balaji VENU ,  Xabier ITURBE ,  Emre ÖZER ,  Antony John PENTON

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry to execute a plurality of code sequences, and configuration storage to store mode control data for the processing circuitry. When the processing circuitry is executing one of said plurality of code sequences, the mode control data is set so as to identify a high resilience mode of operation of the processing circuitry where usage of one or more components of the processing circuitry is modified so as to increase resilience of the processing circuitry to faults relative to a default mode of operation of the processing circuitry.

公开(公告)号：US20180267866A1

公开(公告)日：2018-09-20

申请号：US15463066

申请日：2017-03-20

Applicant: ARM Limited

Inventor： Balaji VENU ,  Xabier ITURBE ,  Emre ÖZER

IPC: G06F11/16 ,  G06F11/18

CPC classification number: G06F11/1641 ,  G06F11/1629 ,  G06F11/184

Abstract: An apparatus comprises at least three processing circuits to perform redundant processing of common program instructions. Error detection circuitry coupled to a plurality of signal nodes of each of said at least three processing circuits comprises comparison circuitry to detect a mismatch between signals on corresponding signal nodes in said at least three processing circuits, the plurality of signal nodes forming a first group of signal nodes and a second group of signal nodes. In response to the mismatch being detected in relation to corresponding signal nodes within the first group, the error detection circuitry is configured to generate a first trigger for a full recovery process for resolving an error detected for an erroneous processing circuit using state information derived from at least two other processing circuits. In response to the mismatch being detected in relation to corresponding signal nodes within the second group the error detection circuitry is configured to generate a second trigger for a targeted recovery process for a subset of components of the erroneous processing circuit. By implementing a targeted recovery process for a subset of components of an erroneous processing circuit a cheaper recovery process may be provided.

公开(公告)号：US20210279124A1

公开(公告)日：2021-09-09

申请号：US17261217

申请日：2019-06-06

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Emre ÖZER ,  Xabier ITURBE ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/07 ,  G06F11/16 ,  G06F11/20 ,  G06F11/30

Abstract: An apparatus comprises a plurality of redundant processing units (4) to perform data processing redundantly in lockstep; common mode fault detection circuitry *6, 22) to detect an event indicative of a potential common mode fault affecting each of the plurality of redundant processing units; a memory (10) shared between the plurality of redundant processing units; and memory checking circuitry (30) to perform a memory scanning operation to scan at least part of the memory for errors; in which the memory checking circuitry (30) performs the memory scanning operation in response to a common mode fault signal generated by the common mode fault detection circuitry (6, 22) indicating that the event indicative of a potential common mode fault has been detected.

公开(公告)号：US20190391888A1

公开(公告)日：2019-12-26

申请号：US16014154

申请日：2018-06-21

Applicant: Arm Limited

Inventor： Milosch MERIAC ,  Xabier ITURBE ,  Emre OZER ,  Balaji VENU ,  Shidhartha DAS

IPC: G06F11/20 ,  G06F11/14 ,  G06F11/16

Abstract: Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

公开(公告)号：US20190012242A1

公开(公告)日：2019-01-10

申请号：US15645053

申请日：2017-07-10

Applicant: ARM LIMITED

Inventor： Emre ÖZER ,  Balaji VENU ,  Xabier ITURBE ,  Antony John PENTON

IPC: G06F11/16

Abstract: An apparatus and method are provided for checking output data during redundant execution of instructions. The apparatus has first processing circuitry for executing a sequence of instructions and second processing circuitry for redundantly executing the sequence of instructions. Error code generation circuitry is used to generate an error code from the first output data generated by the first processing circuitry. Error checking circuitry then uses that error code to perform an error checking operation on redundant output data from the second processing circuitry. As a result of the error checking operation, the error checking circuitry then generates a comparison indication signal to indicate that the first output data differs from the redundant output data when the error checking operation detects an error. This provides a very efficient mechanism for implicitly comparing the output data from the first processing circuitry and the second processing circuitry during redundant execution.

公开(公告)号：US20180129573A1

公开(公告)日：2018-05-10

申请号：US15800145

申请日：2017-11-01

Applicant: ARM Limited

Inventor： Xabier ITURBE ,  Emre OZER ,  Balaji VENU

IPC: G06F11/16 ,  G06F11/18 ,  G06F11/07

CPC classification number: G06F11/1608 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1645 ,  G06F11/1658 ,  G06F11/184 ,  G06F11/187

Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.