公开(公告)号：US20230298158A1

公开(公告)日：2023-09-21

申请号：US18017646

申请日：2021-07-20

Applicant: ASML NETHERLANDS B.V.

Inventor： Jiao HUANG ,  Jinze WANG ,  Hongfei SHI ,  Mu FENG ,  Qian ZHAO ,  Alvin Jianjiang WANG ,  Yan-Jun XIAO ,  Liang LIU

IPC: G06T7/00 ,  G06T7/13

CPC classification number: G06T7/001 ,  G06T7/13 ,  G06T2207/30168 ,  G06T2207/30148 ,  G06T2207/20216 ,  G06T2207/10061

Abstract: A method for selecting good quality images from raw images of a patterned substrate. The method includes obtaining a plurality of raw images (e.g., SEM images) of a patterned substrate; determining a raw image quality metric (e.g., an image score, an average slope, distance between contours) based on data associated with one or more gauges or one or more contours of one or more features within each image of the plurality of raw images, the raw image quality metric being indicative of a raw image quality; and selecting, based on the raw image quality metric, a sub-set of raw images from the plurality of raw images. The sub-set of raw images can be provided for performing more accurate measurements of the one or more features within an image.

公开(公告)号：US20240385530A1

公开(公告)日：2024-11-21

申请号：US18565494

申请日：2022-05-29

Applicant: ASML NETHERLANDS B.V.

Inventor： Jiao HUANG ,  Jinze Wang ,  Yan YAN ,  Yongfa FAN ,  Liang Liu ,  Mu FENG

IPC: G03F7/00

Abstract: Etch bias is determined based on a curvature of a contour in a substrate pattern. The etch bias is configured to be used to enhance an accuracy of a semiconductor patterning process relative to prior patterning processes. In some embodiments, a representation of the substrate pattern is received, which includes the contour in the substrate pattern. The curvature of the contour of the substrate pattern is determined and inputted to a simulation model. The simulation model includes a correlation between etch biases and curvatures of contours. The etch bias for the contour in the substrate pattern is outputted by the simulation model based on the curvature.

公开(公告)号：US20230244152A1

公开(公告)日：2023-08-03

申请号：US18008075

申请日：2021-06-17

Applicant: ASML NETHERLANDS B.V.

Inventor： Jen-Shiang WANG ,  Pengcheng YANG ,  Jiao HUANG ,  Yen-Wen LU ,  Liang LIU ,  Chen ZHANG

IPC: G03F7/00 ,  G03F1/70 ,  G03F7/105

CPC classification number: G03F7/706843 ,  G03F1/70 ,  G03F7/705 ,  G03F7/105

Abstract: A method for determining a likelihood that an assist feature of a mask pattern will print on a substrate. The method includes obtaining (i) a plurality of images of a pattern printed on a substrate and (ii) variance data the plurality of images of the pattern; determining, based on the variance data, a model configured to generate variance data associated with the mask pattern; and determining, based on model-generated variance data for a given mask pattern and a resist image or etch image associated with the given mask pattern, the likelihood that an assist feature of the given mask pattern will be printed on the substrate. The likelihood can be applied to adjust one or more parameters related to a patterning process or a patterning apparatus to reduce the likelihood that the assist feature will print on the substrate.

公开(公告)号：US20230161269A1

公开(公告)日：2023-05-25

申请号：US17919189

申请日：2021-05-07

Applicant: ASML NETHERLANDS B.V.

Inventor： Jiao HUANG ,  Yunan ZHENG ,  Qian ZHAO ,  Jiao LIANG ,  Yongfa FAN ,  Mu FENG

IPC: G03F7/20 ,  G06T7/11

CPC classification number: G03F7/70633 ,  G03F7/70625 ,  G06T7/11 ,  G06T2207/10061

Abstract: Systems and methods for determining one or more characteristic metrics for a portion of a pattern on a substrate are described. Pattern information for the pattern on the substrate is received. The pattern on the substrate has first and second portions. The first portion of the pattern is blocked, for example with a geometrical block mask, based on the pattern information, such that the second portion of the pattern remains unblocked. The one or more metrics are determined for the unblocked second portion of the pattern. In some embodiments, the first and second portions of the pattern correspond to different exposures in a semiconductor lithography process. The semiconductor lithography process may be a multiple patterning technology process, for example, such as a double patterning process, a triple patterning process, or a spacer double patterning process.