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公开(公告)号：US12073114B2
公开(公告)日：2024-08-27
申请号：US17491058
申请日：2021-09-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Hideki Kanayama , Eric M. Scott
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0622 , G06F3/0635 , G06F3/0679
Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.
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Patent Agency Ranking
公开(公告)号：US20230102680A1
公开(公告)日：2023-03-30
申请号：US17491058
申请日：2021-09-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Hideki Kanayama , Eric M. Scott
IPC: G06F3/06
Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.
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公开(公告)号：US11742043B2
公开(公告)日：2023-08-29
申请号：US17506746
申请日：2021-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： YuBin Yao , Eric M. Scott , TieFeng Liu
CPC classification number: G11C29/028 , G06F3/0673 , G11C7/1066 , G11C7/222 , G11C29/023
Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.
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公开(公告)号：US20230144770A1
公开(公告)日：2023-05-11
申请号：US17521578
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric J. Chapman , Stephen Victor Kosonocky , Kaushik Mazumdar , Vydhyanathan Kalyanasundharam , Samuel Naffziger , Eric M. Scott
IPC: G06F1/30
CPC classification number: G06F1/30
Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
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公开(公告)号：US11960340B2
公开(公告)日：2024-04-16
申请号：US17521578
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric J. Chapman , Stephen Victor Kosonocky , Kaushik Mazumdar , Vydhyanathan Kalyanasundharam , Samuel Naffziger , Eric M. Scott
IPC: G06F1/30
CPC classification number: G06F1/30
Abstract: A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.
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公开(公告)号：US20230132306A1
公开(公告)日：2023-04-27
申请号：US17506746
申请日：2021-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： YuBin Yao , Eric M. Scott , TieFeng Liu
IPC: G06F3/06
Abstract: A method for performing read training of a memory channel includes writing a data pattern to a memory using a data bus having a predetermined number of bit lanes. An edge of a read data eye is determined individually for each bit lane by reading the data pattern over the data bus using a read bust cycle having a predetermined length, grouping data received on each bit lane over the read burst cycle to form a bit lane data group, and comparing the bit lane data group to corresponding expected data of the data pattern for each bit lane, logging a phase of each bit lane on which said edge is found, and repeating the reading, grouping, comparing, and logging until the edge is found for all of the bit lanes.
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