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公开(公告)号：US12055991B2
公开(公告)日：2024-08-06
申请号：US17559111
申请日：2021-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Kaushik Mazumdar , Miguel Rodriguez , Mikhail Rodionov , Stephen Victor Kosonocky
CPC classification number: G06F1/28 , H03K3/037 , H03K5/2472 , H03K19/20
Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.
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公开(公告)号：US11630161B1
公开(公告)日：2023-04-18
申请号：US17521601
申请日：2021-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Miguel Rodriguez , Stephen Victor Kosonocky , Kaushik Mazumdar
IPC: G01R31/40 , H03K19/0175 , H03K5/24 , H03M3/00
Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.
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公开(公告)号：US11573593B2
公开(公告)日：2023-02-07
申请号：US15954051
申请日：2018-04-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Richard Martin Born , Stephen Victor Kosonocky , Miguel Rodriguez
Abstract: A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.
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公开(公告)号：US11360504B2
公开(公告)日：2022-06-14
申请号：US15990096
申请日：2018-05-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Stephen Victor Kosonocky
IPC: G06F1/08
Abstract: A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.
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公开(公告)号：US20220091822A1
公开(公告)日：2022-03-24
申请号：US17028723
申请日：2020-09-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Ravinder Reddy Rachala , Stephen Victor Kosonocky , Miguel Rodriguez
Abstract: A multiply-accumulate computation is performed using digital logic circuits. To perform the computation, a plurality of target signals are received at a respective plurality of ripple counters. The counter outputs of the respective ripple counters are scaled by setting stop count values. Counter outputs of the respective ripple counters are adjusted with respective constant values by setting counter reset values at the respective ripple counters. Each count pulses of the target signals for an adjusted period. The count values of the ripple counters are summed. The results may be used to calculate an average value for an adaptive voltage and frequency scaling process.
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Patent Agency Ranking
公开(公告)号：US20190257696A1
公开(公告)日：2019-08-22
申请号：US15902101
申请日：2018-02-22
Applicant: Advanced Micro Devices, Inc.
Inventor： Ravinder Reddy Rachala , Stephen Victor Kosonocky , Stephen C. Ennis
Abstract: A calibrated temperature sensor includes a power on oscillator responsive to a calibration enable signal for providing a power on clock signal, a temperature dependent oscillator responsive to said calibration enable signal for providing a temperature dependent clock signal, and a measurement logic circuit. The measurement logic circuit counts a first number of pulses of the temperature dependent clock signal during a first calibration period using the power on clock signal, a second number of pulses of the temperature dependent clock signal during a second calibration period using a system clock signal, and a third number of pulses of the power on clock signal over a third calibration period using the system clock signal, and a fourth number of pulses of the temperature dependent clock signal using the system clock signal during a normal operation mode, wherein the first calibration period precedes both the second and third calibration periods.
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公开(公告)号：US10366734B2
公开(公告)日：2019-07-30
申请号：US15424418
申请日：2017-02-03
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander W. Schaefer , Ravi T. Jotwani , Samiul Haque Khan , David Hugh McIntyre , Stephen Victor Kosonocky , John J. Wuu , Russell Schreiber
IPC: G11C8/08 , G11C11/418 , G11C5/14 , G11C11/413 , G11C11/419
Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.
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公开(公告)号：US20190229736A1
公开(公告)日：2019-07-25
申请号：US16370479
申请日：2019-03-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen Victor Kosonocky , Mikhail Rodionov , Joyce Cheuk Wai Wong
Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.
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公开(公告)号：US10248177B2
公开(公告)日：2019-04-02
申请号：US14919364
申请日：2015-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Miguel Rodriguez , Stephen Victor Kosonocky
IPC: G06F1/32 , G06F1/30 , G06F1/26 , G06F1/3234 , G06F1/3287
Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.
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公开(公告)号：US11962313B2
公开(公告)日：2024-04-16
申请号：US16370479
申请日：2019-03-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen Victor Kosonocky , Mikhail Rodionov , Joyce Cheuk Wai Wong
CPC classification number: H03L7/0991 , H03K5/14 , H03K2005/00058
Abstract: An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.
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