公开(公告)号：US20180240777A1

公开(公告)日：2018-08-23

申请号：US15956704

申请日：2018-04-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ming HUANG ,  Chun-Hung LIN ,  Yi-Ting CHEN ,  Wen-Hsin LIN ,  Shih-Wei CHAN ,  Yung-Hsing CHANG

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive.

公开(公告)号：US20230207521A1

公开(公告)日：2023-06-29

申请号：US18112463

申请日：2023-02-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hsing CHANG ,  Wen-Hsin LIN

IPC: H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/552

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L23/552 ,  H01L23/3121 ,  H01L25/50

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

公开(公告)号：US20190326256A1

公开(公告)日：2019-10-24

申请号：US15960416

申请日：2018-04-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Hsing CHANG ,  Wen-Hsin LIN

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/552 ,  H01L25/00 ,  H01L21/56

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate with a first surface and a second surface opposite to the first surface, a second substrate adjacent to the first surface of the first substrate, and an encapsulant encapsulating the first substrate and the second substrate. The first substrate defines a space. The second substrate covers the space. The second surface of the first substrate is exposed by the encapsulant. A surface of the encapsulant is coplanar with the second surface of the first substrate or protrudes beyond the second surface of the first substrate.

公开(公告)号：US20140367841A1

公开(公告)日：2014-12-18

申请号：US14303421

申请日：2014-06-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Ming HUANG ,  Chun-Hung LIN ,  Yi-Ting CHEN ,  Wen-Hsin LIN ,  Shih-Wei CHAN ,  Yung-Hsing CHANG

IPC: H01L23/053 ,  H01L23/00

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present disclosure relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. Each of the interconnection elements connects the first substrate and the second substrate. The encapsulation material encapsulates the interconnection elements. The encapsulation material defines a plurality of accommodation spaces to accommodate the interconnection elements, and the profile of each accommodation space is defined by the individual interconnection element, whereby the warpage behavior of the first substrate is in compliance with that of the second substrate during reflow.

Abstract translation: 本公开涉及半导体封装结构和半导体工艺。 半导体封装包括第一衬底，第二衬底，裸片，多个互连元件和封装材料。 每个互连元件连接第一基板和第二基板。 封装材料封装互连元件。 封装材料限定多个容纳空间以容纳互连元件，并且每个容纳空间的轮廓由单独的互连元件限定，由此第一衬底的翘曲行为在回流期间与第二衬底的翘曲行为一致。