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公开(公告)号：US06384398B1
公开(公告)日：2002-05-07
申请号：US09851203
申请日：2001-05-08
IPC分类号： H01L2700
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
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2.发明授权Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture 有权具有多晶硅接触插头的介质型反熔丝电池及其制造方法公开(公告)号：US06362023B1
公开(公告)日：2002-03-26
申请号：US09821232
申请日：2001-03-29
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO2, on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g. bit lines) is formed on the surface of the first insulating layer followed by the formation of a second insulating layer over the poly 1 layer. A contact opening that extends into the poly 1 layer is then created in the second insulating layer and filled with a doped polysilicon contact plug. Next, a dielectric layer is formed on the upper surface of the doped polysilicon contact plug, followed by the formation of a poly 2 layer (e.g. word lines) on the upper surface of the dielectric layer.
摘要翻译： 包括掺杂多晶硅接触插头的基于介质的反熔丝电池和电池阵列，其在编程状态下具有低电阻，低电容和小电池区。 基于电介质的抗熔丝单元包括在半导体衬底的表面上的通常为SiO 2的第一绝缘层。 第一掺杂多晶硅（poly 1）层位于第一绝缘层的上表面上，第二绝缘层在聚1层之上。 掺杂多晶硅接触插塞延伸穿过第二绝缘层并进入聚1层。 通常为ONO或NO电介质复合层的电介质层覆盖掺杂多晶硅接触插塞的上表面。 第二掺杂多晶硅（poly 2）层设置在电介质层上。一种用于制造抗熔丝电池和阵列的工艺包括首先提供半导体衬底并在其表面上形成第一绝缘层。 接下来，在第一绝缘层的表面上形成聚1层（例如位线），然后在聚1层上形成第二绝缘层。 然后在第二绝缘层中形成延伸到聚1层的接触开口，并填充掺杂的多晶硅接触插塞。 接下来，在掺杂多晶硅接触插塞的上表面上形成电介质层，然后在电介质层的上表面上形成聚二层（例如字线）。
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公开(公告)号：US06236082B1
公开(公告)日：2001-05-22
申请号：US09134480
申请日：1998-08-13
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11553
摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.
摘要翻译： 本发明提供一种在集成电路基板上形成成形浮栅的方法。 在集成电路基板的表面中蚀刻沟槽，从而形成尖端。 尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。 然后在衬底表面上形成电介质层并且与沟槽一致。 接下来，在电介质层上方沉积导电层，使其填充沟槽。 然后蚀刻导电层，使得限定浮动栅极。 然后，浮动栅极的底部被沟槽包围。 所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。 衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。 导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。 此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。
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公开(公告)号：US06229739B1
公开(公告)日：2001-05-08
申请号：US09662504
申请日：2000-09-14
IPC分类号： G11C700
CPC分类号： G11C7/065
摘要： A sense amplifier places a low positive voltage, such as 0.1 to 0.3 volts, on a bit line instead of ground when a memory cell is read by utilizing a current source circuit to output a reference current that biases a Schottky diode. The current source circuit is implemented with a Schottky diode that utilizes the reverse-biased leakage current of the diode to form the reference current. The current source circuit can also be implemented with a current mirror circuit.
摘要翻译： 当通过利用电流源电路读出存储单元以输出偏置肖特基二极管的参考电流时，读出放大器将位置线上的低正电压（例如0.1至0.3伏特）置于地线上而不是接地。 电流源电路用肖特基二极管实现，其利用二极管的反向偏置漏电流形成参考电流。 电流源电路也可以用电流镜电路来实现。
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5.发明授权公开(公告)号：US06190968B1
公开(公告)日：2001-02-20
申请号：US09185893
申请日：1998-11-04
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L29/42336 , H01L29/7885
摘要： A method for forming an electrically-programmable read-only-memory (EPROM) or a flash memory cell is disclosed. The EPROM or flash memory cell provides both source-side and drain-side injection, along with a reduced cell size, by forming the memory cell in a trench. The drain is formed in the top surface of the substrate, the source is formed in the bottom surface of the trench, and the stacked gate is formed over the sidewall of the trench.
摘要翻译： 公开了一种形成电可编程只读存储器（EPROM）或闪存单元的方法。 EPROM或闪存单元通过在沟槽中形成存储单元来提供源极侧和漏极侧注入以及减小的单元尺寸。 漏极形成在衬底的顶表面中，源极形成在沟槽的底表面中，并且堆叠的栅极形成在沟槽的侧壁上。
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公开(公告)号：US06177315B1
公开(公告)日：2001-01-23
申请号：US09321702
申请日：1999-05-28
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： An EEPROM cell having a double-poly memory-transistor stacked-gate structure and a double-poly access-transistor stacked-gate structure is formed in a process that utilizes a thick layer of oxide as an etch stop when the layers of material are etched to form the memory-transistor stacked-gate structure and the access-transistor stacked-gate structure.
摘要翻译： 当材料层被蚀刻时，在使用厚层氧化物作为蚀刻停止层的工艺中形成具有双重多晶硅存储晶体管堆叠栅结构和双多晶硅存取晶体管叠层栅结构的EEPROM单元 以形成存储晶体管堆叠栅结构和存取晶体管堆叠栅结构。
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公开(公告)号：US06169310A
公开(公告)日：2001-01-02
申请号：US09205110
申请日：1998-12-03
IPC分类号： H01L2362
CPC分类号： H01L27/0288
摘要： An ESD protection device for use with an integrated circuit that provides a low impedance resistive path between IC pads (including Vdd and Vss pads) when power to the IC is off, while assuring adequate isolation between the IC pads when the power is on. The device includes a semiconductor substrate (typically a p-type Si substrate) and at least two vertically integrated pinch resistors formed in the semiconductor substrate. Each of the vertically integrated pinch resistors is connected to a common electrical discharge line and to a pad. Each of the vertically integrated pinch resistors includes a deep well region and a first surface well region, both of the second conductivity type (typically n-type). The first surface well region circumscribes the deep well region, thereby forming a narrow channel region of the first conductivity type (e.g. p-type) therebetween. When no potential is applied to the first surface well regions (i.e. power is off), the two vertically integrated pinch resistors connected by the common electrical discharge line provide a low impedance resistive path between the pads for shunting ESD current. When a potential is applied to the first surface well region by the IC power supply (i.e. power is on), however, the width of the narrow channel region is pinched-off due to a potential-produced depletion region in the narrow channel region, thereby isolating the pads from each other. A process for the formation of the ESD protection device involves sequential formation of each of the device regions in a semiconductor substrate.
摘要翻译： 一种与集成电路一起使用的ESD保护装置，当IC通电时，在IC焊盘（包括Vdd和Vss焊盘）之间提供低阻抗阻抗路径，同时在电源打开时确保IC焊盘之间的充分隔离。 该器件包括形成在半导体衬底中的半导体衬底（通常为p型Si衬底）和至少两个垂直集成的夹持电阻器。 每个垂直集成的夹持电阻器连接到公共放电线和焊盘。 每个垂直集成的夹持电阻器包括深阱区域和第二表面阱区域，第二导电类型（通常为n型）。 第一表面阱区域围绕深阱区域，从而在其间形成第一导电类型（例如p型）的窄通道区域。 当没有电位施加到第一表面阱区域（即电源关闭）时，通过公共放电线连接的两个垂直集成的夹持电阻器在焊盘之间提供了阻抗ESD阻抗的低阻抗路径，用于分流ESD电流。 然而，当通过IC电源将电势施加到第一表面阱区域（即，电源接通）时，窄通道区域的宽度由于窄沟道区域中的潜在产生的耗尽区而被截断， 从而将焊盘彼此隔离。 用于形成ESD保护装置的方法包括在半导体衬底中顺序地形成每个器件区域。
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8.发明授权Starter current source device with automatic shut-down capability and method for its manufacture 有权具有自动停机功能的起动电流源装置及其制造方法
公开(公告)号：US6078094A
公开(公告)日：2000-06-20
申请号：US196458
申请日：1998-11-19
IPC分类号： H01L27/06 , H01L21/8238 , H01L27/092 , H01L29/80 , H01L29/00
CPC分类号： H01L21/823892 , H01L27/092
摘要： An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-type) on the surface of the substrate that circumscribes the deep well region, and a narrow channel region (typically p-type) separating the deep well region from the first surface well region. The device also includes a first contact region for connecting the first surface well region to the analog circuit, and a second contact region for connecting a substrate region above the deep well to the analog circuit. The configuration provides a variable-width vertical resistor current path capable of starting an analog circuit and then being automatically shut-down by application of a potential to the first contact region sufficient to produce a depletion region that pinches-off the narrow channel region. A process for forming the starter current source device is also provided. The process includes first providing a semiconductor substrate (e.g. p-type), then forming a deep well region (e.g. n-type) below its surface. This is followed by the formation of a first surface well region (e.g. n-type) on the surface of the substrate such that the first surface well region circumscribes the deep well region, thereby producing a narrow channel (e.g. p-type) therebetween. Finally, a first contact region is formed on the surface of the first surface well region, while a second contact region is formed on the surface of semiconductor substrate above the deep well region.
摘要翻译： 具有自动关机功能的模拟电路起动器电流源装置。 该器件包括在其表面下方具有深阱区（通常为n型）的半导体衬底（通常为p型），在衬底的表面上限定深阱区的第一表面阱区（通常为n型） 以及将深阱区域与第一表面阱区域分离的窄通道区域（通常为p型）。 该装置还包括用于将第一表面阱区域连接到模拟电路的第一接触区域和用于将深井上方的衬底区域连接到模拟电路的第二接触区域。 该配置提供了可变宽度的垂直电阻器电流路径，其能够启动模拟电路，然后通过向第一接触区域施加足以产生夹紧窄沟道区域的耗尽区域的电势自动关闭。 还提供了一种用于形成起动器电流源装置的工艺。 该方法包括首先提供半导体衬底（例如p型），然后在其表面下方形成深阱区域（例如n型）。 接着在衬底的表面上形成第一表面阱区域（例如n型），使得第一表面阱区域围绕深阱区域，从而在其间产生窄通道（例如p型）。 最后，在第一表面阱区域的表面上形成第一接触区域，而在深阱区域上方的半导体衬底的表面上形成第二接触区域。
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9.发明授权Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology 有权扩展漏极MOSFET，用于在低电压工艺技术中将集成保险丝元件编程为高电阻公开(公告)号：US06525397B1
公开(公告)日：2003-02-25
申请号：US09376161
申请日：1999-08-17
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.
摘要翻译： 集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。 熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。 施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。 电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。 每个附聚事件会增加保险丝的电阻。 能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。 晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括 多晶硅延伸的阱的表面区域。
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10.发明授权Methods of fabricating floating gate semiconductor device with reduced erase voltage 有权制造具有降低的擦除电压的浮栅半导体器件的方法公开(公告)号：US06368917B1
公开(公告)日：2002-04-09
申请号：US09721604
申请日：2000-11-21
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L27/11553
摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.
摘要翻译： 本发明提供一种在集成电路基板上形成成形浮栅的方法。 在集成电路基板的表面中蚀刻沟槽，从而形成尖端。 尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。 然后在衬底表面上形成电介质层并且与沟槽一致。 接下来，在电介质层上方沉积导电层，使其填充沟槽。 然后蚀刻导电层，使得限定浮动栅极。 然后，浮动栅极的底部被沟槽包围。 所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。 衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。 导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。 此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。
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