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1.发明授权Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology 有权扩展漏极MOSFET，用于在低电压工艺技术中将集成保险丝元件编程为高电阻公开(公告)号：US06525397B1
公开(公告)日：2003-02-25
申请号：US09376161
申请日：1999-08-17
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse. The transistor includes: a well region in a substrate, the well region forming the drain of the transistor; an insulating trench in the well; and a polysilicon gate extending over a portion of the substrate, a portion of the well and a portion of the trench, wherein upon reverse-biasing the junction between the well and the substrate a depletion region is formed which encompasses at least the entire portion of the surface region of the well over which the polysilicon extends.
摘要翻译： 集成的熔丝元件能够被编程为低电压工艺技术中的高电阻。 熔丝包括未掺杂的多晶硅层和硅化物层的堆叠。 施加在堆叠上的电压增加直到发生第一附聚事件，由此在硅化物层中形成不连续性。 电流进一步增加以引起第二聚集事件，从而增加不连续性的大小。 每个附聚事件会增加保险丝的电阻。 能够保持高电压的延伸漏极MOS晶体管与保险丝串联连接，以对熔丝进行编程。 晶体管包括：衬底中的阱区，形成晶体管的漏极的阱区; 井中的绝缘沟槽; 以及在所述衬底的一部分上延伸的多晶硅栅极，所述阱的一部分和所述沟槽的一部分，其中在反向偏置所述阱和所述衬底之间的结点时，形成耗尽区，所述耗尽区至少包括 多晶硅延伸的阱的表面区域。
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2.发明授权Methods of fabricating floating gate semiconductor device with reduced erase voltage 有权制造具有降低的擦除电压的浮栅半导体器件的方法公开(公告)号：US06368917B1
公开(公告)日：2002-04-09
申请号：US09721604
申请日：2000-11-21
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L27/11553
摘要： The present invention provides a method for forming a shaped floating gate on an integrated circuit substrate. A trench is etched in a surface of the integrated circuit substrate such that a tip is formed. The tip may be defined by a first sidewall that is approximately perpendicular to the surface of the integrated circuit substrate and a second sidewall that is disposed at an angle to the surface of the integrated circuit substrate. A dielectric layer is then formed over the substrate surface and conforming to the trench. Next, a conductive layer is deposited above the dielectric layer such that it fills the trench. The conductive layer is then etched such that a floating gate is defined. A bottom portion of the floating gate is then contained by the trench. The resulting floating gate and semiconductor device includes a dielectric layer disposed above an integrated circuit substrate surface. The substrate surface defines a trench having a tip that may be defined by a first sidewall and a second sidewall. A conductive layer is formed above the dielectric layer such that it fills the trench and defines a floating gate having a tip contained by the trench. In addition, a diffusion region may be disposed in the integrated circuit substrate such that the tip of the floating gate points into the diffusion region.
摘要翻译： 本发明提供一种在集成电路基板上形成成形浮栅的方法。 在集成电路基板的表面中蚀刻沟槽，从而形成尖端。 尖端可以由大致垂直于集成电路基板的表面的第一侧壁和与集成电路基板的表面成角度设置的第二侧壁限定。 然后在衬底表面上形成电介质层并且与沟槽一致。 接下来，在电介质层上方沉积导电层，使其填充沟槽。 然后蚀刻导电层，使得限定浮动栅极。 然后，浮动栅极的底部被沟槽包围。 所得的浮栅和半导体器件包括设置在集成电路衬底表面上方的电介质层。 衬底表面限定了具有可由第一侧壁和第二侧壁限定的尖端的沟槽。 导电层形成在电介质层之上，使得它填充沟槽并且限定具有由沟槽包含的尖端的浮动栅极。 此外，可以在集成电路基板中设置扩散区域，使得浮动栅极的尖端指向扩散区域。
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3.发明授权Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up 有权用于形成具有低阈值电压累加的高精度模拟晶体管和具有高阈值电压卷积的数字晶体管的方法公开(公告)号：US06365463B2
公开(公告)日：2002-04-02
申请号：US09316450
申请日：1999-05-21
IPC分类号： H01L21336
CPC分类号： H01L21/823456 , H01L21/82345
摘要： A process for forming high-precision analog transistors with a low threshold voltage roll-up and digital transistors with a high threshold voltage roll-up is disclosed. The process selectively implants the polysilicon layer that forms the gates of the analog transistors so that the doping concentration of the analog gates is greater than the doping concentration of the digital gates.
摘要翻译： 公开了一种用于形成具有低阈值电压卷积的高精度模拟晶体管和具有高阈值电压卷积的数字晶体管的工艺。 该过程选择性地植入形成模拟晶体管的栅极的多晶硅层，使得模拟栅极的掺杂浓度大于数字栅极的掺杂浓度。
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4.发明授权EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming 有权具有源侧注入的EPROM和闪存单元以及在编程期间捕获热电子的栅极电介质公开(公告)号：US06327187B1
公开(公告)日：2001-12-04
申请号：US09665612
申请日：2000-09-18
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0408 , H01L29/4232 , H01L29/792
摘要： An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.
摘要翻译： 具有电可编程只读存储器（EPROM）和具有源极侧注入的闪存单元由栅极电介质材料形成，并且一对栅极都形成在栅极电介质材料上。 栅极电介质材料具有比空穴阱更多的电子陷阱，使得栅极电介质材料能够具有足够的负电位，以在读取操作期间抑制导电通道的形成。
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公开(公告)号：US06208557B1
公开(公告)日：2001-03-27
申请号：US09316445
申请日：1999-05-21
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0408 , H01L29/4232 , H01L29/792
摘要： An electrically-programmable read-only-memory (EPROM) and a flash memory cell having source-side injection are formed with a gate dielectric material, and a pair of gates that are both formed on the gate dielectric material. The gate dielectric material has substantially more electron traps than hole traps so that the gate dielectric material is capable of having a negative potential which is sufficient to inhibit the formation of a conductive channel during a read operation.
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公开(公告)号：US6146962A
公开(公告)日：2000-11-14
申请号：US40212
申请日：1998-03-17
CPC分类号： H01L28/87
摘要： A dynamic random-access-memory (DRAM) cell with a fin or wing-type stacked capacitor is fabricated by using a layer of polysilicon as an etch stop rather than the layer of nitride that is conventionally used. By using the layer of polysilicon, the problem of hydrogen-enhanced boron diffusion in dual work function CMOS transistors is eliminated while at the same time increasing the capacitance of the stacked capacitor without substantially increasing the step height of the capacitor.
摘要翻译： 具有翅片或翼型叠层电容器的动态随机存取存储器（DRAM）单元通过使用多晶硅层作为蚀刻停止而不是常规使用的氮化物层来制造。 通过使用多晶硅层，消除了双功函数CMOS晶体管中的氢增强硼扩散的问题，同时增加了层叠电容器的电容而基本上不增加电容器的台阶高度。
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7.发明授权Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors 有权具有减少数量的存取晶体管的Frohmann-Bentchkowsky EPROM单元的存储器阵列
公开(公告)号：US6137722A
公开(公告)日：2000-10-24
申请号：US301098
申请日：1999-04-28
IPC分类号： G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , H01L27/115 , H01L29/788
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0408 , G11C16/0433 , G11C16/10 , G11C16/26 , H01L27/115 , H01L27/11519 , H01L29/7887 , G11C2216/10 , G11C7/06
摘要： A plurality of Frohmann-Bentchkowsky p-channel memory transistors which are arranged in rows and columns is disclosed. Each column of memory transistors has an associated output line. A row of n-channel MOS access transistors are connected to the output columns to select individual memory transistors in a row of memory transistors.
摘要翻译： 公开了以行和列排列的多个Frohmann-Bentchkowsky p沟道存储晶体管。 每列存储晶体管具有相关联的输出线。 一排n沟道MOS存取晶体管连接到输出列，以选择一排存储晶体管中的各个存储晶体管。
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公开(公告)号：US5982669A
公开(公告)日：1999-11-09
申请号：US185892
申请日：1998-11-04
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11553 , G11C16/0491 , H01L27/115
摘要： An electrically-programmable read-only-memory (EPROM) and a flash memory cell provide both source-side and drain-side injection, along with a reduced cell size, by forming the memory cell in a trench. The drain is formed in the top surface of the substrate, the source is formed in the bottom surface of the trench, and the stacked gate is formed over the sidewall of the trench.
摘要翻译： 电可编程只读存储器（EPROM）和闪存单元通过在沟槽中形成存储单元来提供源侧和漏侧注入以及减小的单元大小。 漏极形成在衬底的顶表面中，源极形成在沟槽的底表面中，并且堆叠的栅极形成在沟槽的侧壁上。
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公开(公告)号：US06384398B1
公开(公告)日：2002-05-07
申请号：US09851203
申请日：2001-05-08
IPC分类号： H01L2700
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
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10.发明授权Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture 有权具有多晶硅接触插头的介质型反熔丝电池及其制造方法公开(公告)号：US06362023B1
公开(公告)日：2002-03-26
申请号：US09821232
申请日：2001-03-29
IPC分类号： H01L2182
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A dielectric-based anti-fuse cell and cell array, that include a doped polysilicon contact plug, with a low resistance in the programmed state, a low capacitance, and a small cell area. The dielectric-based anti-fuse cell includes a first insulating layer, typically SiO2, on the surface of a semiconductor substrate. A first doped polysilicon (poly 1) layer is on the upper surface of the first insulating layer and a second insulating layer is over the poly 1 layer. A doped polysilicon contact plug extends through the second insulating layer and into the poly 1 layer. A dielectric layer, typically either an ONO or NO dielectric composite layer, covers the upper surface of the doped polysilicon contact plug. A second doped polysilicon (poly 2) layer is disposed on the dielectric layer. A process for manufacturing the anti-fuse cell and array includes first providing a semiconductor substrate and forming a first insulating layer on its surface. Next a poly 1 layer (e.g. bit lines) is formed on the surface of the first insulating layer followed by the formation of a second insulating layer over the poly 1 layer. A contact opening that extends into the poly 1 layer is then created in the second insulating layer and filled with a doped polysilicon contact plug. Next, a dielectric layer is formed on the upper surface of the doped polysilicon contact plug, followed by the formation of a poly 2 layer (e.g. word lines) on the upper surface of the dielectric layer.
摘要翻译： 包括掺杂多晶硅接触插头的基于介质的反熔丝电池和电池阵列，其在编程状态下具有低电阻，低电容和小电池区。 基于电介质的抗熔丝单元包括在半导体衬底的表面上的通常为SiO 2的第一绝缘层。 第一掺杂多晶硅（poly 1）层位于第一绝缘层的上表面上，第二绝缘层在聚1层之上。 掺杂多晶硅接触插塞延伸穿过第二绝缘层并进入聚1层。 通常为ONO或NO电介质复合层的电介质层覆盖掺杂多晶硅接触插塞的上表面。 第二掺杂多晶硅（poly 2）层设置在电介质层上。一种用于制造抗熔丝电池和阵列的工艺包括首先提供半导体衬底并在其表面上形成第一绝缘层。 接下来，在第一绝缘层的表面上形成聚1层（例如位线），然后在聚1层上形成第二绝缘层。 然后在第二绝缘层中形成延伸到聚1层的接触开口，并填充掺杂的多晶硅接触插塞。 接下来，在掺杂多晶硅接触插塞的上表面上形成电介质层，然后在电介质层的上表面上形成聚二层（例如字线）。
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