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    Diagnostic circuits and methods for sensor test circuits
    2.
    发明授权
    Diagnostic circuits and methods for sensor test circuits 有权

    公开(公告)号：US11194004B2

    公开(公告)日：2021-12-07

    申请号：US16788505

    申请日：2020-02-12

    Applicant: Allegro MicroSystems, LLC

    Inventor： P. Karl Scheller ,  Devon Fernandez

    IPC: G01R35/00 ,  G01D5/16 ,  G01D5/14

    Abstract: A sensor includes a detector configured to sense a parameter, at least one test circuit configured to detect a respective fault condition of the sensor and generate a fault signal in response to detecting the fault condition, a checker configured to test the at least one test circuit to determine the operational status of the at least one test circuit, and an output signal generator, coupled to receive the sensed parameter, the fault signal, and the operational status of the at least one test circuit. The output signal generator is configured to generate an output signal of the sensor to communicate the sensed parameter and the operational status of the at least one test circuit.

    Output driver having reduced electromagnetic susceptibility and associated methods
    3.
    发明授权
    Output driver having reduced electromagnetic susceptibility and associated methods 有权

    公开(公告)号：US10649481B2

    公开(公告)日：2020-05-12

    申请号：US16259087

    申请日：2019-01-28

    Applicant: Allegro MicroSystems, LLC

    Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

    IPC: G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

    Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

    Output driver having reduced electromagnetic susceptibility and associated methods
    4.
    发明授权
    Output driver having reduced electromagnetic susceptibility and associated methods 有权

    公开(公告)号：US10234887B2

    公开(公告)日：2019-03-19

    申请号：US15161529

    申请日：2016-05-23

    Applicant: Allegro Microsystems, LLC

    Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

    IPC: G06F3/02 ,  G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

    Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

    DIAGNOSTIC CIRCUITS AND METHODS FOR SENSOR TEST CIRCUITS
    10.
    发明申请
    DIAGNOSTIC CIRCUITS AND METHODS FOR SENSOR TEST CIRCUITS 有权

    公开(公告)号：US20210247478A1

    公开(公告)日：2021-08-12

    申请号：US16788505

    申请日：2020-02-12

    Applicant: Allegro MicroSystems, LLC

    Inventor： P. Karl Scheller ,  Devon Fernandez

    IPC: G01R35/00 ,  G01D5/14 ,  G01D5/16

    Abstract: A sensor includes a detector configured to sense a parameter, at least one test circuit configured to detect a respective fault condition of the sensor and generate a fault signal in response to detecting the fault condition, a checker configured to test the at least one test circuit to determine the operational status of the at least one test circuit, and an output signal generator, coupled to receive the sensed parameter, the fault signal, and the operational status of the at least one test circuit. The output signal generator is configured to generate an output signal of the sensor to communicate the sensed parameter and the operational status of the at least one test circuit.

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