公开(公告)号：US20230361223A1

公开(公告)日：2023-11-09

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US20200076189A1

公开(公告)日：2020-03-05

申请号：US16115901

申请日：2018-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H02H9/04 ,  H02H1/00

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

公开(公告)号：US20180342500A1

公开(公告)日：2018-11-29

申请号：US15606043

申请日：2017-05-26

Applicant: Allegro Microsystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L27/02 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L43/06 ,  H01L43/10 ,  H01L29/06 ,  H01L29/08

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US20180061784A1

公开(公告)日：2018-03-01

申请号：US15245699

申请日：2016-08-24

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/60 ,  H01L21/4825 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49589 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2924/19105 ,  H01L2924/00014

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

公开(公告)号：US10468485B2

公开(公告)日：2019-11-05

申请号：US15606043

申请日：2017-05-26

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L29/08 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US20190155322A1

公开(公告)日：2019-05-23

申请号：US16259087

申请日：2019-01-28

Applicant: Allegro MicroSystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H03K19/003 ,  H01L43/02

Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

公开(公告)号：US10147689B2

公开(公告)日：2018-12-04

申请号：US15907445

申请日：2018-02-28

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

公开(公告)号：US11303116B2

公开(公告)日：2022-04-12

申请号：US16115901

申请日：2018-08-29

Applicant: Allegro MicroSystems, LLC

Inventor： Washington Lamar ,  Maxim Klebanov ,  Sundar Chetlur

IPC: H02H9/04 ,  H02H1/00

Abstract: An electronic device having first and second terminals includes an electrical overstress (EOS) protection circuitry configured to detect an EOS event at one or both of the first and second terminals. The electronic device includes a power clamp coupled to the EOS protection circuitry and configured to clamp a voltage between the first terminal and the second terminal to a clamp voltage. The EOS protection circuitry can adjust the clamp voltage when an EOS event is detected.

公开(公告)号：US11195826B2

公开(公告)日：2021-12-07

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.

公开(公告)号：US20210242193A1

公开(公告)日：2021-08-05

申请号：US16776680

申请日：2020-01-30

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Sagar Saxena ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/866

Abstract: In one aspect an electronic device includes a substrate having one of a p-type doping or an n-type doping, a first well in the substrate, a second well in the substrate, a third well in the substrate between the first and second wells, a first terminal connected to the first well, a second terminal connected to the second well, an electrostatic discharge (ESD) clamp connected to the first and second terminals and a transient voltage source connected to the third well. A doping type of the first, second and third wells is the other one of the p-type or n-type doping. The ESD clamp is configured to clamp the first and second wells at a clamp voltage during an ESD event and the transient voltage source is configured to provide a voltage during the ESD event that is less than the clamp voltage.